参数资料
型号: SST55LD017C-40-I-TQW
厂商: SILICON STORAGE TECHNOLOGY INC
元件分类: 存储控制器/管理单元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PQFP100
封装: MS-026AED, TQFP-100
文件页数: 5/52页
文件大小: 606K
代理商: SST55LD017C-40-I-TQW
EOL Product Data Sheet
ATA Flash Disk Controller
SST55LD017A / SST55LD017B / SST55LD017C
13
2006 Silicon Storage Technology, Inc.
S71211-03-EOL
4/06
5.0 SERIAL COMMUNICATION INTERFACE
The Serial Communication Interface is designed to enable the user to restart the self-initialization process and to
customize the Drive Identification Information.
The Serial Communication Interface consists of 4 signals: SCIDOUT, SCIDIN, SCICLK and SCIEN#. Please refer to
the Design Consideration for ATA Flash Disk Controller’s Serial Communication Interface application note for fur-
ther details.
6.0 EXTERNAL CLOCK INTERFACE
The External Clock interface allows an external clock source to drive the ATA flash disk controller. While the controller
has an internal clock source, the External Clock interface allows slowing of the clock operation to limit the peak cur-
rent. Please see the External Clock Operation for ATA Flash Disk Controller application note for further details.
The External Clock interface consists of three signals: INTCLKEN#, EXTCLKIN, and EXTCLKOUT. The INTCLKEN#
pin selects between external and internal clock sources for the ATA flash disk controller. If this pin is pulled low
before device power-up, then the internal clock source is selected; otherwise, the external clock source is selected.
The EXTCLKIN and EXTCLKOUT signals are the input and output clock signals, respectively. Please see Section
12.2 for the detailed circuit schematic.
7.0 CONFIGURABLE WRITE-PROTECT/POWER-DOWN MODES
The WP_PD# pin can be used for either Write-Protect mode or Power-Down mode, but only one mode is active at
any time. Either mode can be selected through the host command, Set-WP_PD#-Mode, explained in Section
Once the mode is set with this command, the device will stay in the configured mode until the next time this com-
mand is issued. Power-off or reset will not change the configured mode.
7.1 Write-Protect Mode
When the device is configured in the Write-Protect mode, the WP_PD# pin offers extended data protection. This fea-
ture can be either selected through a jumper or host logic to protect the stored data from inadvertent system writes or
erases, and viruses. The Write-Protect feature protects the full address space of the data stored on the flash media.
In the Write-Protect mode, the WP_PD# pin should be asserted prior to issuing the destructive commands: Format-
Track, Write-Buffer, Write-Long-Sector, Write-Multiple, Write-Sector(s), or Write-Verify. This will force the ATA flash
disk controller to reject any destructive commands from the ATA interface. All destructive commands will return 51H in
the Status register and 04H in the Error register signifying an invalid command. All non-destructive commands will be
executed normally.
7.2 Power-Down Mode
When the device is configured in the Power-Down mode, if the WP_PD# pin is asserted during a command, the ATA
disk controller completes the current command and returns to the standby mode immediately to save power. After-
wards, the device will not accept any other commands. Only a power-on reset or hardware reset will bring the device
to normal operation with the WP_PD# pin de-asserted.
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