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| 型号： | SSTUAF32869AHLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 锁存器 |
| 英文描述： | 32869 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA150 |
| 封装： | LEAD FREE, BGA-150 |
| 文件页数： | 18/20页 |
| 文件大小： | 452K |
| 代理商： | SSTUAF32869AHLFT |
ICSSSTUAF32869A
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
7
ICSSSTUAF32869A
7095/14
Terminal Functions
Signal
Group
Terminal
Name
Type
Description
Ungated
Inputs
DCKE, DODT
SSTL_18
DRAM function pins not associated with Chip Select
Chip Select
Gated Inputs
D1...D141
1
This range does not include D1, D4, and D7, and their corresponding outputs.
SSTL_18
DRAM inputs, re-driven only when Chip Select is LOW
Chip Select
Inputs
DCS, CSR
SSTL_18
DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one will be
LOW when a valid address/command is present.
Re-Driven
Outputs
Q1A...Q14A1,
Q1B...Q14B1,
QCSnA, B
QCKEnA, B
QODTnA, B
SSTL_18
Outputs of the register, valid after the specified clock count and
immediately following a rising edge of the clock
Parity Input
PARIN
SSTL_18
Input parity is received on pin PARIN, and should maintain odd
parity across the D1:D14 inputs, at the rising edge of the clock,
one cycle after Chip Select is LOW.
Parity Output
PPO
SSTL_18
Partial Parity Output. Indicates parity out of D1-D14.
Parity Error
Output
PTYERR
Open Drain
When LOW, this output indicates that a parity error was
identified associated with the address and/or command inputs.
PTYERR will be active for two clock cycles, and delayed by in
total two clock cycles for compatibility with final parity out timing
on the industry-standard DDR2 register with parity (in JEDEC
definition).
Configuration
Inputs
C1
SSTL_18
When LOW, the register is configured as Register 1. When
HIGH, the register is configured as Register 2.
Clock Inputs
CLK, CLK
SSTL_18
Differential master clock input pair to the register. The register
operation is triggered by a rising edge on the positive clock
input (CLK).
Miscellaneous
Inputs
RESET
SSTL_18
Input
Asynchronous Reset Input. When LOW, it causes a reset of the
internal latches, thereby forcing the outputs LOW. RESET also
resets the PTYERR signal.
VREF
0.9V nominal
Input reference voltage for SSTL_18 inputs. Two pins
(internally tied together) are used for increased
Inputsreliability.
VDD
Power Input
Power Supply Voltage
GND
Ground Input
Ground
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相关代理商/技术参数 |
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| SSTUB32864 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:1.8 V configurable registered buffer for DDR2-800 RDIMM applications |
| SSTUB32864AHLF | 功能描述:IC REGIST BUFF 25BIT DDR2 96-BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:- 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
| SSTUB32864AHLFT | 功能描述:IC REGIST BUFF 25BIT DDR2 96-BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:- 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
| SSTUB32864BHLF | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
| SSTUB32864BHLFT | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
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