参数资料
型号: SSTUAF32869AHLFT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 锁存器
英文描述: 32869 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA150
封装: LEAD FREE, BGA-150
文件页数: 9/20页
文件大小: 452K
代理商: SSTUAF32869AHLFT
ICSSSTUAF32869A
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
17
ICSSSTUAF32869A
7095/14
Test Circuits and Waveforms (VDD = 1.8V ± 0.1V)
Load Circuit: High-to-Low Slew-Rate Adjustment
Voltage Waveforms: High-to-Low Slew-Rate Adjustment
Load Circuit: Low-to-High Slew-Rate Adjustment
Voltage Waveforms: Low-to-High Slew-Rate Adjustment
Load Circuit: Error Output Measurements
Voltage Waveforms: Open Drain Output Low-to-High
Transition Time (with respect to RESET input)
Voltage Waveforms: Open Drain Output High-to-Low
Transition Time (with respect to clock inputs)
Voltage Waveforms: Open Drain Output Low-to-High
Transition Time (with respect to clock inputs)
NOTES:
1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR
≤10MHz, Zo = 50, input
slew rate = 1 V/ns ±20% (unless otherwise specified).
CL =10 pF
RL =50
DUT
Out
Test Point
VDD
VOH
80%
20%
VOL
Output
dv_f
dt_f
CL =10pF
RL =50
DUT
Out
Test Point
VOL
20%
80%
VOH
Output
dv_r
dt_r
CL =10 pF
RL =1K
DUT
Out
Test Point
VDD
VOH
VCC
Output
Waveform 2
LVCMOS
RESET
Input
tPLH
VCC/2
0.15V
0V
VCC
VICR
tHL
Timing
Inputs
VICR
VI(PP)
Output
Waveform 1
VCC/2
VOL
VOH
Output
Waveform 2
0.15V
0V
VICR
tHL
Timing
Inputs
VICR
VI(PP)
相关PDF资料
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