参数资料
型号: SSTUAF32869AHLFT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 锁存器
英文描述: 32869 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA150
封装: LEAD FREE, BGA-150
文件页数: 19/20页
文件大小: 452K
代理商: SSTUAF32869AHLFT
ICSSSTUAF32869A
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
8
ICSSSTUAF32869A
7095/14
Parity and Standby Function Table
Inputs1
Outputs
RESET
DCS
CSR
CLK
Σ of Inputs = H
(D1 - D14)2
PARIN3
PPO
PTYERR4
HL
X
↑↓
Even
L
H
HL
X
↑↓
Odd
L
H
L
HL
X
↑↓
Even
H
L
HL
X
↑↓
Odd
H
L
H
HL
L
↑↓
Even
L
H
HL
L
↑↓
Odd
L
H
L
HL
L
↑↓
Even
H
L
HL
L
↑↓
Odd
H
L
H
HH
H
↑↓
XX
PPOn0
PTYERRn0
H
X
L or H
X
PPOn0
PTYERRn0
LX or
Floating
X or
Floating
X or
Floating
X or
Floating
X or Floating
L
H
1
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
2
This range does not include D1, D4, and D7.
3
PARIN arrives one clock cycle (C1 = 0), or two clock cycles (C1 = 1), after the data to which it applies.
4
This transition assumes PTYERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If
PTYERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. PARIN is used to
generate PPO and PTYERR.
相关PDF资料
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SSTUB32864EC/G 32864 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
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SSTUG32865ET/S SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160
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