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参数资料
| 型号： | SSTUAF32869AHLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 锁存器 |
| 英文描述： | 32869 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA150 |
| 封装： | LEAD FREE, BGA-150 |
| 文件页数： | 3/20页 |
| 文件大小： | 452K |
| 代理商： | SSTUAF32869AHLFT |
ICSSSTUAF32869A
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
11
ICSSSTUAF32869A
7095/14
DC Electrical Characteristics Over Operating Range
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, VDDQ/VDD = 1.8V ± 0.1V.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
VIK
II = -18mA
-1.2
V
VOH
VDDQ = 1.7V, IOH = -100
AVDDQ-0.2
V
VDDQ = 1.7V, IOH = -12mA
1.2
VOL
VDDQ = 1.7V, IOL = 100
A0.2
V
VDDQ = 1.7V, IOL = 12mA
0.5
VERROL
PTYERR Output
Low Voltage
IERROL = 25mA; VDD = 1.7V
0.5
V
IIL
All Inputs
VI = VDD or GND
-5
+5
A
IDD
Static Standby
IO = 0, VDD = 1.9V, RESET = GND
200
A
Static Operating
IO = 0, VDD = 1.9V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK = CLK = VIH(AC)
or VIL(AC)
10
mA
IO = 0, VDD = 1.9V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK = VIH(AC), CLK =
VIL(AC)
120
IDDD
Dynamic
Operating (clock
only)
IO = 0, VDD = 1.8V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK and CLK
switching 50% duty cycle
247
A/Clock
MHz
Dynamic
Operating (per
each data input)
IO = 0, VDD = 1.8V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK and CLK
switching 50% duty cycle. One data
input switching at half clock frequency,
50% duty cycle.
52
A/Clock
MHz/
Data
CIN
Dn, PARIN, DSCn
inputs
VI = VREF ± 250mV
2
3
pF
CLK and CLK
inputs
VICR = 0.9V, VIPP = 600mV
3.5
4.5
RESET
VI = VDD or GND
5
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相关代理商/技术参数 |
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| SSTUB32864BHLF | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
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