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Electrical characteristics
ST10F273M
24.7.1
Conversion timing control
When a conversion is started, first the capacitances of the converter are loaded via the
respective analog input pin to the current analog input voltage. The time to load the
capacitances is referred to as sample time. Next the sampled voltage is converted to a
digital value several successive steps, which correspond to the 10-bit resolution of the ADC.
During these steps the internal capacitances are repeatedly charged and discharged via the
VAREF pin.
The current that has to be drawn from the sources for sampling and changing charges
depends on the time that each respective step takes, because the capacitors must reach
their final voltage level within the given time, at least with a certain approximation. The
maximum current, however, that a source can deliver, depends on its internal resistance.
The time that the two different actions (sampling, and converting) take during conversion
can be programmed within a certain range in the ST10F273M relative to the CPU clock. The
absolute time that is consumed by the different conversion steps therefore is independent
CS
CC
–3.5
pF
RSW
CC
Analog switch resistance
(3)(8)Port5
Port1
–
600
1600
RAD
CC
–
1300
1.
VAREF can be tied to ground when A/D converter is not in use: An extra consumption (around 200A) on
main VDD is added due to internal analog circuitry not completely turned off. Therefore, it is suggested to
maintain the VAREF at VDD level even when not in use, and eventually switch off the A/D converter circuitry
by setting bit ADOFF in ADCON register.
2.
VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in
these cases will be 0x000H or 0x3FFH, respectively.
3.
Not 100% tested, guaranteed by design characterization.
4.
During the sample time the input capacitance CAIN can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS.
After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion
result.
5.
This parameter includes the sample time tS, the time for determining the digital result and the time to load
the result register with the conversion result. Values for the conversion clock tCC depend on programming
6.
DNL, INL, OFS and TUE are tested at VAREF = 5.0 V, VAGND = 0V, VDD = 5.0 V. It is guaranteed by design
characterization for all other voltages within the defined voltage range.
‘LSB’ has a value of VAREF/1024.
For Port5 channels, the specified TUE (± 2LSB) is guaranteed also with an overload condition (see IOV
specification) occurring on maximum 2 not selected analog input pins of Port5 and if the absolute sum of
input overload currents on all Port5 analog input pins does not exceed 10 mA.
For Port1 channels, the specified TUE is guaranteed when no overload condition is applied to Port1 pins:
When an overload condition occurs on maximum 2 not selected analog input pins of Port1 and the input
positive overload current on all analog input pins does not exceed 10 mA (either dynamic or static
injection), the specified TUE is degraded (± 7LSB). To acheive the same accuracy, the negative injection
current on Port1 pins must not exceed -1mA in case of both dynamic and static injection.
7.
The coupling factor is measured on a channel while an overload condition occurs on the adjacent not
selected channels with the overload current within the different specified ranges (for both positive and
negative injection current).
8.
Table 60.
A/D converter characteristics (continued)
Symbol
Parameter
Test condition
Limit values
Unit
Min
Max