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| 型号： | ST10R172LT6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, 50 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, TQFP-100 |
| 文件页数： | 11/68页 |
| 文件大小： | 657K |
| 代理商： | ST10R172LT6 |
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ST10R172L - GENERAL PURPOSE TIMERS
9
GENERAL PURPOSE TIMERS
The GPTs are flexible multifunctional timer/counters used for time-related tasks such as event
timing and counting, pulse width and duty cycle measurements, pulse generation or pulse
multiplication. The GPT unit contains five 16-bit timers, organized in two separate modules,
GPT1 and GPT2. Each timer in each module may operate independently in a number of
different modes, or may be concatenated with another timer of the same module.
9.1
GPT1
Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for one
of four basic modes of operation: timer, gated timer, counter mode and incremental
interface mode. In timer mode, the input clock for a timer is derived from the CPU clock,
divided by a programmable prescaler. In counter mode, the timer is clocked in reference to
external events. Pulse width or duty cycle measurement is supported in gated timer mode
where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For
these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. Table 5 GPT1 timer input frequencies, resolution and periods lists the timer input
frequencies, resolution and periods for each pre-scaler option at 50MHz CPU clock. This also
applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in Timer and
Gated Timer Mode
The count direction (up/down) for each timer is programmable by software or may additionally
be altered dynamically by an external signal on a port pin (TxEUD).
In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be directly connected to the
incremental position sensor signals A and B by their respective inputs TxIN and TxEUD.
Direction and count signals are internally derived from these two input signals so that the
contents of the respective timer Tx corresponds to the sensor position. The third position
sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has output toggle latches (TxOTL) which changes state on each timer over-flow/
underflow. The state of this latch may be output on port pins (TxOUT) e. g. for time out
monitoring of external hardware components, or may be used internally to clock timers T2 and
T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload or
capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are
stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their
associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered
either by an external signal or by a selectable state transition of its toggle latch T3OTL. When
both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL
with the low and high times of a PWM signal, this signal can be constantly generated without
software intervention.
1
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