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参数资料
| 型号： | ST10R172LT6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, 50 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, TQFP-100 |
| 文件页数： | 8/68页 |
| 文件大小： | 657K |
| 代理商： | ST10R172LT6 |
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ST10R172L - INTERRUPT AND TRAP FUNCTIONS
5.2
Hardware traps
Exceptions or error conditions that arise during run-time are called Hardware Traps. Hardware
traps cause immediate non-maskable system reaction similar to a standard interrupt service
(branching to a dedicated vector table location). The occurrence of a hardware trap is
additionally signified by an individual bit in the trap flag register (TFR). Except when another
higher prioritized trap service is in progress, a hardware trap will interrupt any actual program
execution. In turn, hardware trap services can not normally be interrupted by standard or PEC
interrupts. The following table shows all of the possible exceptions or error conditions that can
arise during run-time:
Exception Condition
Trap Flag
Trap Vector
Vector
Location
Trap
Number
Trap
Priority
Reset Functions:
Hardware Reset
RESET
00’0000h
00h
III
Software Reset
RESET
00’0000h
00h
III
Watchdog Timer Overflow
RESET
00’0000h
00h
III
Class A Hardware Traps:
Non-Maskable Interrupt
NMI
NMITRAP
00’0008h
02h
II
Stack Overflow
STKOF
STOTRAP
00’0010h
04h
II
Stack Underflow
STKUF
STUTRAP
00’0018h
06h
II
Class B Hardware Traps:
Undefined opcode
UNDOPC
BTRAP
00’0028h
0Ah
I
Protected instruction fault
PRTFLT
BTRAP
00’0028h
0Ah
I
Illegal word operand access ILLOPA
BTRAP
00’0028h
0Ah
I
Illegal instruction access
ILLINA
BTRAP
00’0028h
0Ah
I
Illegal external bus access
ILLBUS
BTRAP
00’0028h
0Ah
I
Reserved
[2Ch – 3Ch][0Bh – 0Fh]
Software Traps
TRAP Instruction
Any [00’0000h
– 00’01FCh]
steps of 4h
Any
[00h – 7Fh]
Current
CPU
Priority
Table 3 Exceptions or error conditions
1
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