参数资料
型号: ST10R172LT6
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 16-BIT, 50 MHz, MICROCONTROLLER, PQFP100
封装: 14 X 14 MM, TQFP-100
文件页数: 38/68页
文件大小: 657K
代理商: ST10R172LT6
43/68
ST10R172L - ELECTRICAL CHARACTERISTICS
15.3.3 Multiplexed Bus
VDD = 3.3 V ± 0.3 V
VSS = 0 V
TA = -40°C to +85 °C
CL = 50 pF
ALE cycle time = 6 TCL + 2
tA + tC + tF (60 ns at 50-MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 50 MHz
Variable CPU Clock
1/2TCL = 1 to 50 MHz
Un
it
min.
max.
min.
max.
ALE high time
t5
CC
7 +
tA
TCL - 3 +
tA
–ns
Address (P1, P4), BHE
setup to ALE
t6
CC
3 +
tA
TCL - 7 +
tA
–ns
Address (P0) setup to ALE
t6m
CC
5 +
tA
TCL - 5 +
tA
–ns
Address hold after ALE
t7
CC
5 +
tA
TCL - 5 +
tA
–ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC
5 +
tA
TCL - 5 +
tA
–ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC
-5 +
tA
-5 +
tA
–ns
Address float after RD,
(with RW-delay)1)
t10
CC
51
51
ns
Address float after RD,
(no RW-delay)1
t11
CC
151
TCL + 51
ns
RD, WR low time
(with RW-delay)
t12
CC
13 +
tC
2TCL - 7+
tC
–ns
RD, WR low time
(no RW-delay)
t13
CC
23 +
tC
3TCL - 7 +
tC
–ns
RD to valid data in
(with RW-delay)
t14
SR
5 +
tC
2TCL - 15
+
tC
ns
RD to valid data in
(no RW-delay)
t15
SR
15 +
tC
3TCL - 15
+
tC
ns
ALE low to valid data in
t16
SR
15
+
tA + tC
3TCL - 15
+
tA + tC
ns
Address to valid data in
t17
SR
20
+ 2
tA + tC
4TCL - 20
+ 2
tA + tC
ns
Table 14 Multiplexed bus
1
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