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参数资料
| 型号： | ST62P35BQ6/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP52 |
| 封装： | PLASTIC, QFP-52 |
| 文件页数： | 47/82页 |
| 文件大小： | 617K |
| 代理商： | ST62P35BQ6/XXX |
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ST62T35B/E35B
CONTROL REGISTERS (Cont’d)
Status Control Register 4 (SCR4)
Address: E3h - Read/Write/Clear only
Bit7- Bit4 = Reserved, set to 0.
Bit 3 = OVFPOL.
Overflow Output Polarity. This bit
defines the polarity for the Overflow Output OVF.
When 0, OVF is set on every overflow event if en-
abled in Set mode (OVFEN = 1, OVFMD = 0). The
reset state of OVF is 0.
When 1, OVF is reset on every overflow event if
enabled in Set mode.
The reset state of OVF is 1.
Bit 2 = OVFEN.
Overflow Output Enable. This bit
enables the Overflow output OVF. When 0 the
Overflow output is disabled: if OVFPOL = 0, the
state of OVF is 0, if OVFPOL = 1, the state of
OVF = 1.The Overflow Output is enabled when
this bit = 1, it must be set to use the OVF output.
Bit 1 = PWMPOL.
PWM Output Polarity. This bit
defines the polarity for the PWM Output PWM.
When 0, PWM is set on every Masked-Counter
Zero event and is reset on a Masked-Compare if
enabled in Set/Reset mode (PWMEN = 1, PWM-
MD = 0).
The reset state of PWM pin is 0 When 1, OVF is
set on every Masked-Compare event and is reset
on a Masked-Counter Zero event if enabled in
Set/Reset mode (PWMEN = 1, PWMMD = 0).
The reset state of PWM is 1.
Bit 0 = PWMEN.
PWM Output Enable. This bit en-
ables the PWM output PWM. When 0 the PWM
output is disabled: if PWMPOL = 0, the state of
PWM is 0, if PWMPOL = 1, the state of PWM = 1.
The PWM Output is enabled when this bit = 1, it
must be set to use the PWM output.
Notes:
A Masked-Compare is the logical AND of the
Mask Register MASK with the Counter Register
CT, compared with the logical AND of the com-
pare
Register
CMP:
[(MASK
&
CT)
=
(MASK&CMP)].
A Masked-Counter Zero is the logical AND of the
Mask Register MASK with the Counter Register
CT, compared with zero: [(MASK & CT) = 0000h].
4.3.6 16-BIT REGISTERS
Note: Care must be taken when using single-bit
instructions (RES/SET/INC/DEC) 16-bit registers
(RLCP, CP, CMP, MSK) since these instructions
imply a READ-MODIFY-WRITE operation on the
register. As the ST6 is based on a 8-bit architec-
ture, to write a 16-bit register, the high byte must
be written first to an intermediate register (latch
register) and the whole 16-bit register is loaded at
the same time as the low byte is written. A WRITE
operation of the HIGH byte is performed on the in-
termediate register (latch register) but a READ op-
eration of the HIGH byte is directly performed on
the 16-bit register (last loaded value). As a conse-
quence, it is always mandatory to write the LOW
byte before any single-bit instruction on the HIGH
byte in order to load the value set in the intermedi-
ate register to the 16-bit register (refresh the 16-bit
register).
Example:
The following sequence is NOT GOOD:
ldi t16cmph, 055h
ldi t16cmpl, 000h
; t16cm p (16-bit register )=55 00h
ldi t16cmph, 0AAh
; t16cm p (16-bit register )=55 00h
inc t16cmph
; t16cm p (16-bit register )=55 00h
ldi t16cmpl, 000h
; t16cm p (16-bit register )=56 00h
; and NOT AB00h
The CORRECT sequence is:
ldi t16cmph, 055h
ldi t16cmpl, 000h
; t16cm p (16-bit register )=55 00h
ldi t16cmph, 0AAh
; t16cm p (16-bit register )=55 00h
ldi t16cmpl, 000h
; t16cm p (16-bit register )=AA 00h
inc t16cmph
; t16cm p (16-bit register )=AA 00h
ldi t16cmpl, 000h
;t16cmp (16-bit regis ter) =AB0 0h
70
Res.
Res. Res. Res.
OVFPO
L
OVFEN PMPOL
PWME
N
50
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