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参数资料
| 型号： | ST62P35BQ6/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP52 |
| 封装： | PLASTIC, QFP-52 |
| 文件页数： | 51/82页 |
| 文件大小： | 617K |
| 代理商： | ST62P35BQ6/XXX |
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ST62T35B/E35B
4.5 U. A. R. T. (Universal Asynchronous Receiver/Transmitter)
The UART provides the basic hardware for asyn-
chronous serial communication which, combined
with an appropriate software routine, gives a serial
interface providing communication with common
baud rates (up to 38,400 Baud with an 8MHz ex-
ternal oscillator) and flexible character formats.
Operating in Half-Duplex mode only, the UART
uses 11-bit characters comprising 1 start bit, 9 data
bits and 1 Stop bit. Parity is supported by software
only for transmit and for checking the received par-
ity bit (bit 9). Transmitted data is sent directly, while
received data is buffered allowing further data
characters to be received while the data is being
read out of the receive buffer register. Data trans-
mit has priority over data being received.
The UART is supplied with an MCU internal clock
that is also available in WAIT mode ofthe processor.
4.5.1 PORTS INTERFACING
RXD reception line and TXD emission line are
sharing the same external pins as two I/O lines.
Therefore, UART configuration requires to set
these two I/O lines through the relevant ports reg-
isters. The I/O line common with RXD line must be
defined as input mode (with or without pull-up)
while the I/O line common with TXD line must be
defined as output mode (Push-pull or open drain).
The transmitted data is inverted and can therefore
use a single transistor buffering stage. Defined as
input, the RXD line can be read at any time as an
I/O line during the UART operation. The TXD pin
follows I/O port registers value when UARTOE bit
is cleared, which means when no serial transmis-
sion is in progress. As a consequence, a perma-
nent high level has to be written onto the I/O port
in order to achieve a proper stop condition on the
TXD line when no transmission is active.
Figure 31. UART Block Diagram
C
O
NT
RO
L
O
G
IC
TO
C
O
R
E
STA RT
DETE CTOR
DATA SHIFT
REGISTER
D8 D7 D6 D5 D4 D3 D2 D1 D0
CONTROL REGISTER
BAUD RATE
RECEIVE BUFFE R
REGISTER
PROGRAMMABLE
DIVI DER
DIN
DOUT
D9
BAUD RATE x 8
WRITE
READ
RXD1
TXD1
UARTOE
RX and TX
INTERRUPTS
TXD
DR
0
MUX
1
fOSC
VR02009
54
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