参数资料
型号: ST72652C4T1/XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, MICROCONTROLLER, PQFP48
封装: 7 X 7 MM, ROHS COMPLIANT, TQFP-48
文件页数: 32/161页
文件大小: 2656K
代理商: ST72652C4T1/XXX
ST72651AR6
127/161
Doc ID 7215 Rev 4
OPERATING CONDITIONS (Cont’d)
13.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for VDD, fOSC, and TA.
Notes:
1. Not tested, guaranteed by construction.
2. The VDD rise time condition is needed to insure a correct device power-on and LVD reset. Not tested in production.
13.3.3 Power Supply Manager Characteristics
Subject to general operating conditions for VDD, fOSC, and TA. Not tested on LVD devices (without E suf-
fix).
1. Not tested, guaranteed by construction.
2. A protection diode is present between VDDF and USBVDD. Refer to Section 6.4.2.1 and section 6.4.2.2 on page 33 for
further information.
13.3.4 Storage Device Supply Characteristics
Subject to general operating conditions for VDD, fOSC, and TA.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIT+
Reset release threshold
(VDD rise)
2.9
3.5
3.8
V
VIT-
Reset generation threshold
(VDD fall)
2.6
3.1
3.5
Vhys
LVD voltage threshold hysteresis
VIT+-VIT-
150
300
mV
fCUTOFF
LVD filter cut-off frequency 1)
Not detected by the LVD
10
MHz.
VtPOR
VDD rise time
2)
0.3
10
ms
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
USBVIT+
USB Voltage detector high threshold
(USBVDD rise)
2)
3.50
3.80
4.00
V
USBVIT-
USB Voltage detector low threshold
(USBVDD fall)
2)
3.30
3.65
3.80
USBVhys
USB voltage threshold hysteresis
USBVIT+-USBVIT-
100
200
300
mV
VPLLmin48
Minimum voltage required for stable
48MHz PLL operation (PLL locked)
3.7 1)
V
VPLLmin40
Minimum voltage required for
40MHz PLL operation (PLL un-
locked)
3.4 1)
V
VPLLmin24
Minimum voltage required for
24MHz PLL operation (PLL un-
locked)
3.0 1)
V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDF
Voltage output for external storage
device (Iload max = 50mA)
USB Mode: VSET[1:0]=11
2.5
2.8
3.2
V
10
2.9
3.3
3.6
01
3.0
3.4
3.8
00
3.1
3.5
3.9
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