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参数资料
型号： ST72C171K2B6
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32
封装： SHRINK, PLASTIC, DIP-32
文件页数： 6/152页
文件大小： 2156K
代理商： ST72C171K2B6
ST72C171
103/152
8-BIT A/D CONVERTER (ADC) (Cont’d)
7.9.3.2 Digital A/D Conversion Result
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (VAIN) is greater than or equal
to VDDA (high-level voltage reference) then the
conversion result in the DR register is FFh (full
scale) without overflow indication.
If input voltage (VAIN) is lower than or equal to
VSSA (low-level voltage reference) then the con-
version result in the DR register is 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.
RAIN is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
7.9.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion
phases as shown in Figure 56:
s
Sample capacitor loading [duration: tLOAD]
During this phase, the VAIN input voltage to be
measured is loaded into the CADC sample
capacitor.
s
A/D conversion [duration: tCONV]
During this phase, the A/D conversion is
computed (8 successive approximations cycles)
and the CADC sample capacitor is disconnected
from the analog input pin to get the optimum
analog to digital conversion accuracy.
While the ADC is on, these two phases are contin-
uously repeated.
At the end of each conversion, the sample capaci-
tor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.
7.9.3.4 Software Procedure
Refer to the control/status register (CSR) and data
register (DR) in Section 7.9.6 for the bit definitions
and to Figure 56 for the timings.
ADC Configuration
The total duration of the A/D conversion is 12 ADC
clock periods (1/fADC=2/fCPU).
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the I/O
ports chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the CSR register:
– Select the CH[3:0] bits to assign the analog
channel to be converted.
ADC Conversion
In the CSR register:
– Set the ADON bit to enable the A/D converter
and to start the first conversion. From this time
on, the ADC performs a continuous conver-
sion of the selected channel.
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
valid until the next conversion has ended.
A write to the CSR register (with ADON set) aborts
the current conversion, resets the COCO bit and
starts a new conversion.
Figure 56. ADC Conversion Timings
7.9.4 Low Power Modes
Note: The A/D converter may be disabled by reset-
ting the ADON bit. This feature allows reduced
power consumption when no conversion is needed
and between single shot conversions.
7.9.5 Interrupts
None
Mode
Description
WAIT
No effect on A/D Converter
HALT
A/D Converter disabled.
After wakeup from Halt mode, the A/D Con-
verter requires a stabilisation time before ac-
curate conversions can be performed.
ADCCSR WRITE
ADON
COCO BIT SET
tLOAD
tCONV
OPERATION
HOLD
CONTROL
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相关代理商/技术参数
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ST72C215G2M3 制造商:STMicroelectronics 功能描述:MCU 8-Bit ST7 CISC 8KB Flash 3.3V/5V 28-Pin SO Tube 制造商:STMicroelectronics 功能描述:MCU 8BIT ST7 CISC 8KB FLASH 3.3V/5V 28SOIC - Rail/Tube
ST72C215G2M5 制造商:STMicroelectronics 功能描述:MCU 8BIT ST7 CISC 8KB FLASH 3.3V/5V 28SOIC - Rail/Tube
ST72C215G2M6 功能描述:8位微控制器 -MCU Flash 8K SPI RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
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