
Device configuration and ordering information
ST7L34, ST7L35, ST7L38, ST7L39
Doc ID 11928 Rev 7
6:4
OSCRANGE[2:0]
Oscillator range
When the internal RC oscillator is not selected (option OSC = 1),
these option bits select the range of the resonator oscillator current
source or the external clock source.
000: Typ. frequency range with resonator (LP) = 1~2 MHz
001: Typ. frequency range with resonator (MP) = 2~4 MHz)
010: Typ. frequency range with resonator (MS) = 4~8 MHz)
011: Typ. frequency range with resonator (HS) = 8~16 MHz)
100: Typ. frequency range with resonator (VLP) = 32.768~ kHz)
101: External clock on OSC1
110: Reserved
111: External clock on PB4
Note: OSCRANGE[2:0] has no effect when AWUCK option is set to 0.
In this case, the VLP oscillator range is automatically selected
as AWU clock
3:2
-
Reserved, must be set to 1
1ROP_R
Readout protection for ROM
This option is for read protection of ROM
0: Readout protection off
1: Readout protection on
0ROP_D
Readout protection for data EEPROM
This option is for read protection of EEPROM memory.
0: Readout protection off
1: Readout protection on
Table 134.
Option byte 1 description
Bit
Bit name
Function
7
-
Reserved, must be set to 1(1)
6PLLOFF
PLL disable
This option bit enables or disables the PLL.
0: PLL enabled
1: PLL disabled (bypassed)
5
-
Reserved, must be set to 0
(1)4OSC
RC oscillator selection
This option bit enables selection of the internal RC oscillator.
0: RC oscillator on
1: RC oscillator off
Note: To improve clock stability and frequency accuracy when the RC
oscillator is selected, it is recommended to place a decoupling
capacitor, typically 100 nF, between the VDD and VSS pins as
close as possible to the ST7 device.
3:2
LVD[1:0]
Low voltage selection
These option bits enable the voltage detection block (LVD and AVD)
with a selected threshold to the LVD and AVD:
11: LVD off
10: LVD on (highest voltage threshold)
Table 133.
Option byte 0 description
Bit
Bit name
Function