
Power saving modes
ST7L34, ST7L35, ST7L38, ST7L39
Doc ID 11928 Rev 7
9.4.1
Halt mode recommendations
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Make sure that an external event is available to wake up the microcontroller from halt
mode.
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When using an external interrupt to wake up the microcontroller, re-initialize the
corresponding I/O as ‘input pull-up with interrupt’ or ‘floating interrupt’ before executing
the HALT instruction. The main reason for this is that the I/O may be incorrectly
configured due to external interference or by an unforeseen logical condition.
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For the same reason, re-initialize the level sensitiveness of each external interrupt as a
precautionary measure.
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The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in program memory with
the value 0x8E.
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As the HALT instruction clears the interrupt mask in the CC register to allow interrupts,
the user may choose to clear all pending interrupt bits before executing the HALT
instruction. This avoids entering other peripheral interrupt routines after executing the
external interrupt routine corresponding to the wakeup event (reset or external
interrupt).
9.5
Active halt mode
Active halt mode is the lowest power consumption mode of the MCU with a real-time clock
(RTC) available. It is entered by executing the ‘HALT’ instruction. The decision to enter either
in active halt or halt mode is given by the LTCSR/ATCSR register status as shown in the
following table:
The MCU exits in active halt mode on reception of a specific interrupt (see
Table 14:●
When exiting active halt mode by means of a reset, a 256 CPU cycle delay occurs.
After the startup delay, the CPU resumes operation by fetching the reset vector which
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When exiting active halt mode by means of an interrupt, the CPU immediately resumes
When entering active halt mode, the I bit in the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately (see
Figure 28,
Table 18.
LTCSR/ATCSR register status
LTCSR1 TB1IE
bit
ATCSR OVFIE
bit
ATCSRCK1
bit
ATCSRCK0
bit
Meaning
0x
x
0
Active halt mode disabled
00
x
1x
x
Active halt mode enabled
x1
0
1