
ST7L34, ST7L35, ST7L38, ST7L39
On-chip peripherals
Doc ID 11928 Rev 7
It uses six registers:
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3 control registers: SCICR1, SCICR2 and SCICR3
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2 status registers: SCISR register and LHLR register mapped at the SCIERPR address
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A baud rate register: LPR mapped at the SCIBRR address and an associated fraction
register LPFR mapped at the SCIETPR address
The bits dedicated to LIN are located in the SCICR3. Refer to the register descriptions in
Entering LIN mode
To use the LINSCI in LIN mode the following configuration must be set in SCICR3 register:
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Clear the M bit to configure 8-bit word length.
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Set the LINE bit.
Master
To enter master mode the LSLV bit must be reset In this case, setting the SBK bit will send
13 low bits.
Then the baud rate can programmed using the SCIBRR, SCIERPR and SCIETPR registers.
In LIN master mode, the conventional and/or extended prescaler define the baud rate (as in
standard SCI mode)
Slave
Set the LSLV bit in the SCICR3 register to enter LIN slave mode. In this case, setting the
SBK bit will have no effect.
In LIN slave mode the LIN baud rate generator is selected instead of the conventional or
extended prescaler. The LIN baud rate generator is common to the transmitter and the
receiver.
Then the baud rate can be programmed using LPR and LPRF registers.
Note:
It is mandatory to set the LIN configuration first before programming LPR and LPRF,
because the LIN configuration uses a different baud rate generator from the standard one.
LIN transmission
In LIN mode the same procedure as in SCI mode has to be applied for a LIN transmission.
To transmit the LIN header the proceed as follows:
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First set the SBK bit in the SCICR2 register to start transmitting a 13-bit LIN synch
break
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Reset the SBK bit
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Load the LIN synch field (0x55) in the SCIDR register to request synch field
transmission
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Wait until the SCIDR is empty (TDRE bit set in the SCISR register)
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Load the LIN message Identifier in the SCIDR register to request Identifier
transmission.