
On-chip peripherals
ST7L34, ST7L35, ST7L38, ST7L39
Doc ID 11928 Rev 7
Figure 68.
LSF bit set and clear
3LHDM
LIN header detection method
This bit is set and cleared by software. It is only usable in LIN slave mode. It
enables the header detection method. In addition if the RWU bit in the SCICR2
register is set, the LHDM bit selects the wake-up method (replacing the WAKE
bit).
0: LIN synch break detection method
1: LIN identifier field detection method
2LHIE
LIN header interrupt enable
This bit is set and cleared by software. It is only usable in LIN slave mode.
0: LIN header interrupt is inhibited
1: An SCI interrupt is generated whenever LHDF = 1
1
LHDF
LIN header detection flag
This bit is set by hardware when a LIN header is detected and cleared by a
software sequence (an access to the SCISR register followed by a read of the
SCICR3 register). It is only usable in LIN slave mode.
0: No LIN header detected
1: LIN header detected
Note: The header detection method depends on the LHDM bit:
- If LHDM = 0, a header is detected as a LIN synch break
- If LHDM = 1, a header is detected as a LIN Identifier, meaning that a LIN
synch break field + a LIN synch field + a LIN identifier field have been
consecutively received.
0LSF
LIN synch field state
This bit indicates that the LIN synch field is being analyzed. It is only used in LIN
slave mode. In auto synchronization mode (LASE bit = 1), when the SCI is in the
LIN synch field state it waits or counts the falling edges on the RDI line.
It is set by hardware as soon as a LIN synch break is detected and cleared by
hardware when the LIN synch field analysis is finished (see
Figure 68). This bit
can also be cleared by software to exit LIN Synch state and return to idle mode.
0: The current character is not the LIN synch field
1: LIN synch field state (LIN synch field undergoing analysis)
Table 73.
SCICR3 register description (continued)
Bit
Name
Function
LIN synch
Identifier
Parity bits
field
break
11 dominant bits
LSF bit