
ST7L34, ST7L35, ST7L38, ST7L39
On-chip peripherals
Doc ID 11928 Rev 7
Control register 3 (SCICR3)
SCICR3
Reset value: 0000 0000 (00h)
76
543
21
0
LDUM
LINE
LSLV
LASE
LHDM
LHIE
LHDF
LSF
R/W
Table 73.
SCICR3 register description
Bit
Name
Function
7
LDUM
LIN divider update method
This bit is set and cleared by software and is also cleared by hardware (when
RDRF = 1). It is only used in LIN slave mode. It determines how the LIN divider
can be updated by software.
0: LDIV is updated as soon as LPR is written
(if no auto synchronization update occurs at the same time)
1: LDIV is updated at the next received character (when RDRF = 1)
after a write to the LPR register
Note: If no write to LPR is performed between the setting of LDUM bit and the
reception of the next character, LDIV is updated with the old value.
After LDUM has been set, it is possible to reset the LDUM bit by software.
In this case, LDIV can be modified by writing into LPR/LPFR registers.
6:5 LINE, LSLV
LIN mode enable bits
These bits configure the LIN mode:
0x: LIN mode disabled
10: LIN master mode
11: LIN slave mode
The LIN master configuration enables sending of LIN synch breaks (13 low
bits) using the SBK bit in the SCICR2 register.
The LIN slave configuration enables:
The LIN slave baud rate generator. The LIN divider (LDIV) is then represented by
the LPR and LPFR registers. The LPR and LPFR registers are read/write
accessible at the address of the SCIBRR register and the address of the
SCIETPR register.
Management of LIN headers
LIN synch break detection (11-bit dominant)
LIN wake-up method (see LHDM bit) instead of the normal SCI wake-up method
Inhibition of break transmission capability (SBK has no effect)
LIN parity checking (in conjunction with the PCE bit)
4
LASE
LIN auto synch enable
This bit enables the auto synch unit (ASU). It is set and cleared by software. It is
only usable in LIN slave mode.
0: Auto synch unit disabled
1: Auto synch unit enabled