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参数资料
型号： ST7FLITE19BF0B6
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP20
封装： 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-20
文件页数： 139/159页
文件大小： 2855K
代理商： ST7FLITE19BF0B6
ST7LITE1xB
80/159
LITE TIMER (Cont’d)
11.3.3 Functional Description
11.3.3.1 Timebase Counter 1
The 8-bit value of Counter 1 cannot be read or
written by software. After an MCU reset, it starts
incrementing from 0 at a frequency of fOSC/32. An
overflow event occurs when the counter rolls over
from F9h to 00h. If fOSC = 8 MHz, then the time pe-
riod between two counter overflow events is 1 ms.
This period can be doubled by setting the TB bit in
the LTCSR1 register.
When Counter 1 overflows, the TB1F bit is set by
hardware and an interrupt request is generated if
the TB1IE bit is set. The TB1F bit is cleared by
software reading the LTCSR1 register.
11.3.3.2 Input Capture
The 8-bit input capture register is used to latch the
free-running upcounter (Counter 1) 1 after a rising
or falling edge is detected on the LTIC pin. When
an input capture occurs, the ICF bit is set and the
LTICR register contains the counter 1 value. An in-
terrupt is generated if the ICIE bit is set. The ICF
bit is cleared by reading the LTICR register.
The LTICR is a read-only register and always con-
tains the data from the last input capture. Input
capture is inhibited if the ICF bit is set.
11.3.3.3 Timebase Counter 2
Counter 2 is an 8-bit autoreload upcounter. It can
be read by accessing the LTCNTR register. After
an MCU reset, it increments at a frequency of
fOSC/32 starting from the value stored in the
LTARR register. A counter overflow event occurs
when the counter rolls over from FFh to the
LTARR reload value. Software can write a new
value at any time in the LTARR register, this value
will be automatically loaded in the counter when
the next overflow occurs.
When Counter 2 overflows, the TB2F bit in the
LTCSR2 register is set by hardware and an inter-
rupt request is generated if the TB2IE bit is set.
The TB2F bit is cleared by software reading the
LTCSR2 register.
Figure 52. Input Capture Timing Diagram.
04h
8-bit COUNTER 1
t
01h
fOSC/32
xxh
02h
03h
05h
06h
07h
04h
LTIC PIN
ICF FLAG
LTICR REGISTER
CLEARED
4s
(@ 8 MHz fOSC)
fCPU
BY S/W
07h
READING
LTIC REGISTER
1
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相关代理商/技术参数
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