参数资料
型号: ST7FLITE19BF0B6
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP20
封装: 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-20
文件页数: 85/159页
文件大小: 2855K
代理商: ST7FLITE19BF0B6
ST7LITE1xB
31/159
7.6 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low voltage Detector (LVD) and Auxiliary Volt-
age Detector (AVD) functions. It is managed by
the SICSR register.
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to section 12.2.1 on page 107 for further de-
tails.
7.6.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) gener-
ates a static reset when the VDD supply voltage is
below a VIT-(LVD) reference value. This means that
it secures the power-up as well as the power-down
keeping the ST7 in reset.
The VIT-(LVD) reference value for a voltage drop is
lower than the VIT+(LVD) reference value for power-
on in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup-
ply (hysteresis).
The LVD Reset circuitry generates a reset when
VDD is below:
–VIT+(LVD)when VDD is rising
–VIT-(LVD) when VDD is falling
The LVD function is illustrated in Figure 18.
The voltage threshold can be configured by option
byte to be low, medium or high.
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is above VIT-(LVD), the
MCU can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
The LVD allows the device to be used without any
external RESET circuitry.
The LVD is an optional function which can be se-
lected by option byte.
Use of LVD with capacitive power supply: with this
type of power supply, if power cuts occur in the ap-
plication, it is recommended to pull VDD down to
0V to ensure optimum restart conditions. Refer to
circuit example in Figure 106 on page 136 and
note 4.
It is recommended to make sure that the VDD sup-
ply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func-
tions properly.
Figure 18. Low Voltage Detector vs Reset
VDD
VIT+(LVD)
RESET
VIT-(LVD)
Vhys
1
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