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参数资料
型号： ST7FLITE19BF0B6
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP20
封装： 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-20
文件页数： 5/159页
文件大小： 2855K
代理商： ST7FLITE19BF0B6
ST7LITE1xB
102/159
ANALOG COMPARATOR (Cont’d)
11.6.4 Register Description
Internal Voltage Reference Register (VREFCR)
Read/Write
Reset Value : 0000 0000 (00h)
Bit 7 = VCEXT External Voltage Reference for
Comparator
This bit is set or cleared by software. It is used to
connect the external reference voltage to the VN
comparator input.
0: External reference voltage not connected to VN
1: External reference voltage connected to VN
Bit 6 = VCBGR Bandgap Voltage for Comparator
This bit is set or cleared by software. It is used to
connect the bandgap voltage of 1.2V to the VN
comparator input.
0: Bandgap voltage not connected to VN
1: Bandgap voltage connected to VN
Bits 5:2 = VR[3:0] Programmable Internal Voltage
Reference Range Selection
These bits are set or cleared by software. They are
used to select one of 16 different voltages availa-
ble from the internal voltage reference module and
connect it to comparator input VN.
Refer to Table 20.
Table 20. Voltage Reference Programming
Bits 1:0 = Reserved, Must be kept cleared.
Comparator Control Register (CMPCR)
Read/Write
Reset Value : 1000 0000 (80h)
Bit 7= CHYST Comparator Hysteresis Enable
This bit is set or cleared by software and set by
hardware reset. When this bit is set, the compara-
tor hysteresis is enabled.
0: Hysteresis disabled
1: Hysteresis enabled
Note: To avoid spurious toggling of the output of
the comparator due to noise on the voltage refer-
ence, it is recommended to enable the hysteresis.
Bit 6 = Reserved, Must be kept cleared
Bit 5 = CINV Comparator Output Inversion Select
This bit is set or cleared by software and cleared
by hardware reset. When this bit is set, the compa-
rator output is inverted.
If interrupt enable bit CMPIE is set in the CMPCR
register, the CINV bit is also used to select which
type of level transition on the comparator output
will generate the interrupt. When this bit is reset,
interrupt will be generated at the rising edge of the
comparator output change (COMP signal, refer to
Figure 62 on page 101). When this bit is set, inter-
rupt will be generated at the falling edge of compa-
rator output change (COMP signal, refer to Figure
62 on page 101).
0: Comparator output not inverted and interrupt
generated at the rising edge of COMP
1: Comparator output inverted and interrupt gener-
ated at the falling edge of COMP
70
VCEXT VCBGR
VR3
VR2
VR1
VR0
0
VCEXT
bit
VCBGR
bit
VR3
bit
VR2
bit
VR1
bit
VR0
bit
VN Voltage
1
x
VEXT
0
1
x
1.2 bandgap
0
11
3.2V
0
11
10
3V
0
11
01
2.8V
0
11
00
2.6V
0
10
11
2.4V
0
10
2.2V
0
10
01
2V
0
10
00
1.8V
0
01
11
1.6V
0
01
10
1.4V
0
1
0
1
1.2V
00
0
1
0
1V
0
1
0.8V
0
1
0
0.6V
0
1
0.4V
0
0.2V
70
CHY-
ST
0
CINV CMPIF CMPIE
CMP
COUT CMPON
VCEXT
bit
VCBGR
bit
VR3
bit
VR2
bit
VR1
bit
VR0
bit
VN Voltage
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