- 您现在的位置：买卖IC网 > PDF目录69378 > ST7PL35F2UA/XXXE (STMICROELECTRONICS) 8-BIT, MROM, 8 MHz, MICROCONTROLLER, QCC20 PDF资料下载
参数资料
| 型号： | ST7PL35F2UA/XXXE |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, QCC20 |
| 封装： | 5 X 6 MM, ROHS COMPLIANT, QFN-20 |
| 文件页数： | 167/168页 |
| 文件大小： | 2955K |
| 代理商： | ST7PL35F2UA/XXXE |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页当前第167页第168页
Obsolete
Product(s)
- Obsolete
Product(s)
ST7L34, ST7L35, ST7L38, ST7L39
98/168
LINSCI
SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
CONTROL REGISTER 2 (SCICR2)
Read/Write
Reset Value: 0000 0000 (00h)
1)This bit has a different function in LIN mode, please
refer to the LIN mode register description.
Bit 7 = TIE Transmitter interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: In SCI interrupt is generated whenever
TDRE = 1 in the SCISR register
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1
in the SCISR register
Bit 5 = RIE Receiver interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1
or RDRF = 1 in the SCISR register
Bit 4 = ILIE Idle line interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
IDLE = 1 in the SCISR register.
Bit 3 = TE Transmitter enable
This bit enables the transmitter. It is set and
cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
– During transmission, a “0” pulse on the TE bit
(“0” followed by “1”) sends a preamble (idle line)
after the current word.
– When TE is set there is a 1 bit-time delay before
the transmission starts.
Bit 2 = RE Receiver enable
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled in the SCISR register
1: Receiver is enabled and begins searching for a
start bit
Bit 1 = RWU Receiver wake-up
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
Notes:
– Before selecting Mute mode (by setting the RWU
bit) the SCI must first receive a data byte, other-
wise it cannot function in Mute mode with wake-
up by Idle line detection.
– In Address Mark Detection Wake-Up configura-
tion (WAKE bit = 1) the RWU bit cannot be mod-
ified by software while the RDRF bit is set.
Bit 0 = SBK Send break
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
DATA REGISTER (SCIDR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 55).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 55).
70
TIE
TCIE
RIE
ILIE
TE
RE
RWU
1)
SBK1)
70
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
1
相关PDF资料 |
PDF描述 |
|---|---|
| ST7L35F2UA/XXXRE | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, QCC20 |
| ST7L35F2UC/XXXRE | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, QCC20 |
| ST7L39F2MC/XXXE | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO20 |
| ST7L39F2UC/XXXRE | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, QCC20 |
| ST7PL34F2MC/XXXE | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST7PLITE02F0U6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT MICROCONTROLLER WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI |
| ST7PLITE02Y0B6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT MICROCONTROLLER WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI |
| ST7PLITE02Y0B6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI |
| ST7PLITE02Y0M6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI |
| ST7PLITE02Y0M6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI |
发布紧急采购，3分钟左右您将得到回复。