参数资料
型号: ST7PL35F2UA/XXXE
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, QCC20
封装: 5 X 6 MM, ROHS COMPLIANT, QFN-20
文件页数: 22/168页
文件大小: 2955K
代理商: ST7PL35F2UA/XXXE
Obsolete
Product(s)
- Obsolete
Product(s)
ST7L34, ST7L35, ST7L38, ST7L39
118/168
10-BIT A/D CONVERTER (ADC) (cont’d)
11.6.3.2 Digital A/D Conversion Result
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (VAIN) is greater than VDDA
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).
If the input voltage (VAIN) is lower than VSSA (low-
level voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD-
CDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
RAIN is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
11.6.3.3 A/D Conversion
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the “I/O ports”
chapter. Using these pins as analog inputs does
not affect the ability of the port to be read as a logic
input.
In the ADCCSR register:
– Select the CS[2:0] bits to assign the analog
channel to convert.
ADC Conversion mode
In the ADCCSR register:
Set the ADON bit to enable the A/D converter and
to start the conversion. From this time on, the
ADC performs a continuous conversion of the
selected channel.
When a conversion is complete:
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit.
To read the 10 bits, perform the following steps:
1. Poll EOC bit
2. Read ADCDRL
3. Read ADCDRH. This clears EOC automati-
cally.
To read only 8 bits, perform the following steps:
1. Poll EOC bit
2. Read ADCDRH. This clears EOC automati-
cally.
11.6.4 Low Power Modes
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed and between single shot conversions.
11.6.5 Interrupts
None.
Mode
Description
WAIT
No effect on A/D Converter
HALT
A/D Converter disabled.
After wakeup from Halt mode, the A/D
Converter requires a stabilization time
tSTAB (see Electrical Characteristics)
before accurate conversions are per-
formed.
相关PDF资料
PDF描述
ST7L35F2UA/XXXRE 8-BIT, MROM, 8 MHz, MICROCONTROLLER, QCC20
ST7L35F2UC/XXXRE 8-BIT, MROM, 8 MHz, MICROCONTROLLER, QCC20
ST7L39F2MC/XXXE 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO20
ST7L39F2UC/XXXRE 8-BIT, MROM, 8 MHz, MICROCONTROLLER, QCC20
ST7PL34F2MC/XXXE 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO20
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