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参数资料
| 型号： | STP1080ABGA-83 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA256 |
| 封装： | PLASTIC, BGA-256 |
| 文件页数： | 17/22页 |
| 文件大小： | 124K |
| 代理商： | STP1080ABGA-83 |
194
STP1080A
Companion Device for 167/200 MHz UltraSPARC-I Systems
UltraSPARC-I Data Buffer (UDB-I)
July 1997
There is no automatic updating of memory when a single-bit ECC error is corrected. Software may update
memory with corrected data, maintaining MP cache coherency, by using cache ushes and
Compare-And-Swap.
Data is protected on the CPU side using parity (odd parity), and on the system side using ECC. Parity is gen-
erated for data going from the UDB to the CPU, while ECC bits are generated for data going from the UDB to
the UPA. Data coming to the UDB from the CPU is checked for parity errors, while data coming from the UPA
to the UDB is checked for ECC.
ECC Code Used
ECC is performed on a 64-bit boundary, using Kaneda SEC/DED/S4ED codes. There are eight check bits per
64-bit boundary. The code provides detection of single and double bit errors, as well as three and four bit
errors within a nibble. In addition, the code provides correction of any single bit error on 64-bit data.
ECC Control and Status Registers
Memory is not updated after correcting an error. Parity error is detected by the XOR of the eight P_syndrome
bits. During ECC checking, the syndrome for the rst correctable error is logged, and is only overwritten by
the syndrome for an uncorrectable error. When there is an uncorrectable error, bad parity is forced onto data
going out to the CPU. In diagnostic mode, a check bit vector of ECC bits is forced for data going from UDB to
UPA.
1. This register is cleared to 0 at power-on reset; W1C implies write-1-to-clear.
TABLE 2: ECC Status Denition [1]
Field
Description
Type
CE
Correctable Error
W1C
UE
Uncorrectable Error
W1C
E_Syndrome
ECC syndrome bits, 64 bits -> 8 bits
R
TABLE 3: ECC Control and Diagnostic Register Denition
Field
Description
Type
Version
Software-accessible Version Number ==TAP_IDreg[31:28]
R
FMODE
Force Check Bit Vector for data to UPA
RW
FCBV
Forced Check Bit Vector
RW
Reserved
Figure 3. ECC and Parity Fault Status Register (Duplicated in UDB_H and UDB_L)
CE
UE
E_SYNDROME[7:0]
Reserved
Figure 4. ECC Control and Diagnostic Register (Duplicated in UDB_H and UDB_L)
Version[3:0]
FMODE
FCBV[7:0]
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