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参数资料
| 型号： | STP1080ABGA-83 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA256 |
| 封装： | PLASTIC, BGA-256 |
| 文件页数： | 21/22页 |
| 文件大小： | 124K |
| 代理商： | STP1080ABGA-83 |
198
STP1080A
Companion Device for 167/200 MHz UltraSPARC-I Systems
UltraSPARC-I Data Buffer (UDB-I)
July 1997
Transactions on the DataBus are controlled by the System Controller (SC) to UltraSPARC-I ReplyBus.
The data_stall signal from the UPA allows the system controller to control the ow of data to or from that
UPA port. It is typically used to allow memory several cycles of setup on the UPA bus, or to ask the UPA port
to hold data longer, so that it can be held at memory longer.
Clocking
Processor/Interconnect Clock Relationship
The ratio of the processor to interconnect clock can be either 2:1 or 3:1. UDB operates at interconnect
frequency.
Testability
The UDB implements the IEEE 1149.1 standard, to aid in board level testing. Boundary Scan Description Lan-
guage (BSDL) is available for the device.
External Power Down
The power down mode is intended to support Energy Star compliance. The EPD pin initiates an internal
reset, stops the clock and PLL, and UDB enters power-down mode. Exiting power down mode is similar to
normal power-up sequence.
1. Opcodes with * imply the UDB-I takes no action.
TABLE 5: S_REPLY[3:0] Encodings [1]
S_REPLY
Mnemonic
Action
0000
s_idle
Default
0001*
s_err
Bus error
0010
s_sack
Coherence read block: UDB => snoop buffer (64B)
0011
s_wbcan
Writeback cancel: incr. wrback buffer readctr by 4
0100
s_was
Write ack single: UDB => non-cacheable store
0101
s_wab
Write ack block: UDB => wrback/block_store/interrupt send
0110*
s_oak
Ownership ack block
0111*
s_inak
Interrupt nack
1000
s_rbu
Read block unshared: UDB <= read ll (64B)
1001
s_rbs
Read block shared: UDB <= read ll (64B)
1010
s_ras
Read ack single: read ll (16B)
1011*
s_rto
Read time-out
1101
s_swib
Slave write interrupt block: UDB <= interrupt receive
1110
s_srs
Slave read single: UDB => read_portid
1111*
s_srb
Slave read block
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