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参数资料
| 型号： | STR635FZ1T6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 36 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封装： | 20 X 20 MM, TQFP-144 |
| 文件页数： | 14/51页 |
| 文件大小： | 1485K |
| 代理商： | STR635FZ1T6 |
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STR73xF
Block Diagram
21/51
2.3
Memory Mapping
Figure 5 shows the various memory configurations of the STR73xF system. The system
memory map (from 0x0000_0000 to 0xFFFF_FFFF) is shown on the left part of the figure,
the right part shows maps of the Flash and APB areas. For flexibility the Flash or RAM
addresses can be aliased to Block 0 addresses using the remapping feature
Most reserved memory spaces (gray shaded areas in Figure 5) are protected from access
by the user code. When an access this memory space is attempted, an ABORT signal is
generated. Depending on the type of access, the ARM processor will enter “prefetch abort”
state (Exception vector 0x0000_000C) or “data abort” state (Exception vector
0x0000_0010). It is up to the application software to manage these abort exceptions.
Figure 5.
Memory map
FLASH Memory Space
64K/128/256 Kbytes
APB BRIDGE 1 REGS
Addressable Memory Space
0
1
2
3
4
1K
5
6
7
0x1FFF FFFF
0x2000 0000
0x3FFF FFFF
0x4000 0000
0x5FFF FFFF
0x6000 0000
0x7FFF FFFF
0x8000 0000
0x9FFF FFFF
0xA000 0000
0xBFFF FFFF
0xC000 0000
0xDFFF FFFF
0xE000 0000
0xFFFF FFFF
0xFFFF 8000
0xFFFF 83FF
0xFFFF 8400
0xFFFF 87FF
0xFFFF 8800
0xFFFF 8BFF
0xFFFF 8C00
0xFFFF 8FFF
0xFFFF 9000
0xFFFF 93FF
0xFFFF 9400
0xFFFF 97FF
0xFFFF 9800
0xFFFF 9BFF
0xFFFF 9C00
0xFFFF 9FFF
0xFFFF A000
0xFFFF A3FF
0xFFFF A800
0xFFFF ABFF
0xFFFF AC00
0xFFFF AFFF
0xFFFF B000
0xFFFF C3FF
0xFFFF C400
0xFFFF C7FF
0xFFFF C800
0xFFFF CBFF
0xFFFF CC00
0xFFFF D000
0xFFFF FFFF
1K
0x0010 0017
0x6000 03FF
0x0000 0000
APB Memory Space
4 Gbytes
32 Kbytes
FLASH (1)
64K/128K/256K
PRCCU
1K
APB TO ARM7
BRIDGE
0xFFFF 8000
32K
EIC
0xFFFF FC00
1K
APB BRIDGE 0 REGS
0xFFFF FBFF
0xFFFF CFFF
CONFIG. REGS
64B
Drawing not to scale
0x4000 003F
FLASH
0x8010 0017
64K/128K/256K
0xFFFF C000
0xFFFF D400
0xFFFF D3FF
0xFFFF D800
0xFFFF D7FF
0xFFFF DC00
0xFFFF DBFF
0xFFFF E000
0xFFFF DFFF
0xFFFF E400
0xFFFF E3FF
0xFFFF E800
0xFFFF E7FF
0xFFFF EC00
0xFFFF EBFF
1K
I2C 0
reserved
TB 0-2
UART 0
UART 1
TIM 0
TIM 1
CAN 0(4)
CAN 1(4)
CAN 2(4)
PWM 0-5
GP I/O 0-6
BSPI 0
BSPI 1
BSPI 2
DMA 0-3
RTC
ADC
0xFFFF F800
0xFFFF F7FF
0xFFFF F400
0xFFFF F3FF
0xFFFF F000
0xFFFF EFFF
0xFFFF B3FF
0xFFFF B400
0xFFFF B7FF
0xFFFF B800
RAM
16K
1K
0xFFFF BBFF
TIM 2
TIM 3
TIM 4
TIM 5-9
reserved
WAKEUP
reserved
1K
0xFFFF BFFF
0xFFFF BC00
I2C 1
access to gray shaded area will return an ABORT
B0F5(3)
0x8000 1FFF
0x8000 0000
0x8000 2000
0x8000 3FFF
0x8000 4000
0x8000 5FFF
0x8000 6000
0x8000 7FFF
0x8000 8000
0x8000 FFFF
0x8001 0000
0x8001 FFFF
0x8010 0000
0x8010 0017
0x8010 C000
0x8010 DFFF
8K
32K
8K
20B
64K
B0F4
Flash registers
NATIVE ARBITER
16B
B0F6(2)
0x8002 0000
0x8002 FFFF
64K
B0F7(2)
0x8003 0000
0x8003 FFFF
64K
UART 2
UART 3
0xFFFF 9E00
0xFFFF A200
CMU
0xFFFF F600
0x2000 000F
System Memory
B0F3
B0F2
B0F1
B0TF
1K
(1) FLASH aliased at 0x0000 0000h by system decoder for booting with valid instruction upon RESET from Block B0 (8 Kbytes)
0xFFFF A400
0xFFFF A7FF
1K
WDG
WAKEUPTIM
0xFFFF A600
0xA000 3FFF
(2) Only available in STR73xZ2/V2
(3) Only available in STR73xZ2/V2 and STR73xZ1/V1
(4) Only available in STR730/STR731
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