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参数资料
型号： SY89230UMG
厂商： Micrel Inc
文件页数： 10/15页
文件大小： 0K
描述： IC CLOCK DIVIDER LVPECL 16-MLF
标准包装： 100
系列： Precision Edge®
类型： 时钟除法器
PLL： 无
输入： CML，LVDS，PECL
输出： LVPECL
电路数： 1
比率 - 输入:输出： 1:1
差分 - 输入:输出： 是/是
频率 - 最大： 3.2GHz
除法器/乘法器： 是/无
电源电压： 2.375 V ~ 3.6 V
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 16-VFQFN 裸露焊盘，16-MLF?
供应商设备封装： 16-MLF?（3x3）
包装： 管件
产品目录页面： 1090 (CN2011-ZH PDF)
其它名称： 576-2112-5
576-2112-5-ND
576-2964-5
4
Copyright 2005 Cirrus Logic, Inc.
DS651UM23
Version 2.3
CobraNet Hardware User’s Manual
List of Figures
Figure 1. CobraNet Data Services ......................................................................................................... 5
Figure 2. CobraNet Interface Hardware Block Diagram......................................................................... 8
Figure 3. Audio Clock Sub-system....................................................................................................... 17
Figure 4. Channel Structure for Synchronous Serial Audio at 64FS (One Sample Period) -
CS18100x/CS49610x & CS18101x/CS49611x ............................................................ 19
Figure 5. Channel Structure for Synchronous Serial Audio at 128FS (One Sample Period) -
CS18102x/CS49612x ................................................................................................... 19
Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1..................................... 20
Figure 7. Serial Port Data Timing Overview......................................................................................... 20
Figure 8. Audio Data Timing Detail - Normal Mode, 64FS -
CS18100x/CS49610x, CS18101x/CS49611x .............................................................. 21
Figure 9. Audio Data Timing Detail - Normal Mode, 128FS -
CS18102x/CS49612x ................................................................................................... 21
Figure 10. Audio Data Timing Detail - I2S Mode, 64FS -
CS18100x/CS49610x, CS18101x/CS49611x .............................................................. 21
Figure 11. Audio Data Timing Detail - I2S Mode, 128FS -
CS18102x & CS49612x................................................................................................ 21
Figure 12. Audio Data Timing Detail - Standard Mode, 64FS -
CS18100x/CS49610x, CS18101x/CS49611x .............................................................. 22
Figure 13. Audio Data Timing Detail - Standard Mode, 128FS -
CS18102x/CS49612x ................................................................................................... 22
Figure 14. Host Port Read Cycle Timing - Motorola Mode .................................................................. 25
Figure 15. Host Port Write Cycle Timing - Motorola Mode................................................................... 25
Figure 16. Parallal Control Port - Intel Mode Read Cycle .................................................................... 27
Figure 17. Parallel Control Port - Intel Mode Write Cycle .................................................................... 27
Figure 18. CM-2 Module Assembly Drawing, Top ............................................................................... 38
Figure 19. CM-2 Module Assembly Drawing, Bottom .......................................................................... 39
Figure 20. General PCB Dimensions ................................................................................................... 40
Figure 21. Example Configuration, Side View...................................................................................... 41
Figure 22. Faceplate Dimensions ........................................................................................................ 42
Figure 23. Connector Detail ................................................................................................................. 43
Figure 24. CM-2 RevF Schematic Page 1 of 7 .................................................................................... 44
Figure 25. CM-2 RevF Schematic Page 2 of 7 .................................................................................... 45
Figure 26. CM-2 RevF Schematic Page 3 of 7 .................................................................................... 46
Figure 27. CM-2 RevF Schematic Page 4 of 7 .................................................................................... 47
Figure 28. CM-2 RevF Schematic Page 5 of 7 .................................................................................... 48
Figure 29. CM-2 RevF Schematic Page 6 of 7 .................................................................................... 49
Figure 30. CM-2 RevF Schematic Page 7 of 7 .................................................................................... 50
Figure 31. 144-Pin LQFP Package Drawing ........................................................................................ 51
Figure 32. Device Part Numbering Explanation ................................................................................... 53
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相关代理商/技术参数
参数描述
SY89230UMG TR 功能描述:时钟驱动器及分配 Divide-by-3 and 5 LVPECL Clock Divider with Internal Termination and FSI (3.2GHz) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel
SY89230UMGTR 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.2GHz Precision, LVPECL ÷3, ÷5 Clock Divider
SY89231U 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:1GHz Precision, LVPECL ±3, ±5 Clock Divider with Fail-Safe Input and Internal Termination
SY89231UMG 功能描述:时钟驱动器及分配 Divide-by-3 and 5 LVDS Clock Divider with Internal Termination and FSI (3.2GHz) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel
SY89231UMG TR 功能描述:时钟驱动器及分配 Divide-by-3 and 5 LVDS Clock Divider with Internal Termination and FSI (3.2GHz) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel
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