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参数资料
| 型号： | T431616D |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| 中文描述： | 100万× 16内存为512k × 16Bit的X 2Banks同步DRAM |
| 文件页数： | 34/74页 |
| 文件大小： | 781K |
| 代理商： | T431616D |
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TE
CH
tm
T431616D/E
TM Technology Inc. reserves the right
P. 4
Publication Date: FEB. 2007
to change products or specifications without notice.
Revision: A
Pin Descriptions (Table 1. Pin Details of T431616D/E)
Symbol
Type
Description
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
CKE
Input
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes low
synchronously with clock(set-up and hold time same as other inputs), the internal clock is
suspended from the next clock cycle and the state of output and burst address is frozen as long as
the CKE remains low. When both banks are in the idle state, deactivating the clock controls the
entry to the Power Down and Self Refresh modes. CKE is synchronous except after the device
enters Power Down and Self Refresh modes, where CKE becomes asynchronous until exiting the
same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh
modes, providing low standby power.
A11
Input
Bank Select: A11(BS) defines to which bank the BankActivate, Read, Write, or BankPrecharge
command is being applied.
A0-A10
Input
Address Inputs: A0-A10 are sampled during the BankActivate command (row address A0-A10)
and Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select
one location out of the 256K available in the respective bank. During a Precharge command, A10
is sampled to determine if both banks are to be precharged (A10 = HIGH). The address inputs also
provide the op-code during a Mode Register Set command.
CS#
Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder.
All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection
on systems with multiple banks. It is considered part of the command code.
RAS#
Input
Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the
CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and CS# are
asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or the
Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the
BankActivate command is selected and the bank designated by BS is turned on to the active state.
When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by
BS is switched to the idle state after the precharge operation.
CAS#
Input
Column Address Strobe: The CAS# signal defines the operation commands in conjunction with
the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is held
"HIGH" and CS# is asserted "LOW," the column access is started by asserting CAS# "LOW."
Then, the Read or Write command is selected by asserting WE# "LOW" or "HIGH."
WE#
Input
Write Enable: The WE# signal defines the operation commands in conjunction with the RAS#
and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select the
BankActivate or Precharge command and Read or Write command.
LDQM,
UDQM
Input
Data Input/Output Mask: LDQM and UDQM are byte specific, nonpersistent I/O buffer
controls. The I/O buffers are placed in a high-z state when LDQM/UDQM is sampled HIGH.
Input data is masked when LDQM/UDQM is sampled HIGH during a write cycle. Output data is
masked (two-clock latency) when LDQM/UDQM is sampled HIGH during a read cycle. UDQM
masks DQ15-DQ8, and LDQM masks DQ7-DQ0.
DQ0-DQ15
Input/Output Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of CLK.
The I/Os are byte-maskable during Reads and Writes.
NC
-
No Connect: These pins should be left unconnected.
VDDQ
Supply
DQ Power: Provide isolated power to DQs for improved noise immunity. ( 3.3V
± 0.3V )
VSSQ
Supply
DQ Ground: Provide isolated ground to DQs for improved noise immunity. ( 0 V )
VDD
Supply
Power Supply: +3.3V
± 0.3V
VSS
Supply
Ground
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相关代理商/技术参数 |
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| T431616D-5C | 制造商:TMT 制造商全称:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T431616D-5CG | 制造商:TMT 制造商全称:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T431616D-5S | 制造商:TMT 制造商全称:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T431616D-5SG | 制造商:TMT 制造商全称:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T431616D-6C | 制造商:TMT 制造商全称:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
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