参数资料
型号: TDA8754HL/21/C1
厂商: NXP SEMICONDUCTORS
元件分类: ADC
英文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封装: 20 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, SOT486-1, LQFP-144
文件页数: 10/57页
文件大小: 259K
代理商: TDA8754HL/21/C1
TDA8754_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 3 May 2007
18 of 57
NXP Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msample/s
8.9 3-level
When the synchronization pulse of the input of the SOG is 3-level, the system will be able
to detect that a 3-level sync is present and will advise the customer if a change is
observed by setting bit HPDO = 1 and pin HPDO = HIGH. It is possible to disable this
function with bit FTRILEVEL. When this automatic function is disabled, the manual mode
will only inuence the separator circuitry.
9.
I2C-bus register description
9.1 I2C-bus formats
9.1.1 Write 1 register
Each register is programmed independently by giving its subaddress and its data content.
Table 6.
I2C-bus sequence for writing 1 register
SDA line
Description
S
master starts with a start condition
Byte 1
master transmits device address (7 bits) plus write command bit (R/W=0)
A
slave generates an acknowledge
Byte 2
master transmits programming mode and register subaddress to write to
A
slave generates an acknowledge
Byte 3
master transmits data 1
A
slave generates an acknowledge
P
master generates a stop condition
Table 7.
Byte format for writing 1 register
Bits
7
6
5
4
3
2
1
0
Byte 1
device address
R/W
A6
A5
A4
A3
A2
A1
A0
-
100110
X
0
Byte 2
programming mode
register subaddress
-
MODE
SA4
SA3
SA2
SA1
SA0
X
0
-----
Byte 3
data 1
D7
D6
D5
D4
D3
D2
D1
D0
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