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参数资料
| 型号： | TDA8754HL/21/C1 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封装： | 20 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, SOT486-1, LQFP-144 |
| 文件页数： | 8/57页 |
| 文件大小： | 259K |
| 代理商： | TDA8754HL/21/C1 |
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TDA8754_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 3 May 2007
16 of 57
NXP Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msample/s
that the values HSYNCL, HBACKL and HDISPL (see Figure 5) are even value. If an odd
value is entered the outputs HSYNCO and DEO can change state during falling edge,
which is not compliant with the th(o) and td(o) specied output timing.
Bit SCHCKREFO is used if in demultiplexed mode one pixel shift is needed in the DEO
signal (to move the screen one vertical line). By setting bit SCHCKREFO from a logic 0 to
a logic 1 a left move is obtained, also the timing relationship between HSYNCO, DEO and
CKDATA stays unchanged. An even number of pixel moves is done by changing the value
of HBACKL and HSYNCL. The correct combination of bits HBACKL, HSYNCL and
SCHCKREFO places the rst active pixel at the beginning of the screen with always the
correct phase relationship between outputs DEO, HSYNCO and CKDATA.
Bit HSOSEL should be set to a logic 0 only after the PLL is stable, so only after the video
standard has been found and correct PLL parameters have been set in the TDA8754. Bit
HSOSEL should be set to a logic 1 to have a stable HSYNCO signal during the video
recognition. The video standard can be recognized by using the signals FIELDO,
VSYNCO and HSYNCO. The phase relation between CKDATA and HSYNCO (or DEO) is
undened if bit HSOSEL = 1.
8.4 PLL
The ADCs are clocked by either the internal PLL locked to the reference clock (Hsync
from input or Hsync from sync separator) or to an external clock connected to pin CKEXT.
This selection is performed via the I2C-bus by setting bit CKEXT. To use the external
clock, bit CKEXT must be reset to logic 1.
The PLL phase frequency detector can be disconnected during the frame yback (vertical
blanking) or the unavailability of the Ckref signal by using the coast function. The coast
signal can be derived from the VSYNC1(2) input, from the Vsync extracted by the sync
separator or from the coast input. The coast function can be disabled with bit COE.
The coast signal may be active either HIGH or LOW by setting bit COS.
It is possible to control the phase of the ADC clock via the I2C-bus with the included digital
phase-shift controller. The phase register (5 bits) enables to shift the phase by steps of
11.25 deg.
The PLL also provides a CKDATA clock. This clock is synchronized with the data outputs
whatever the output mode is.
It is possible to delay the CKDATA clock with a constant delay (t = 2 ns compared to the
outputs) by setting bit DLYCLKRGB = 1. Moreover, it is possible to invert this output by
setting bit CKDATINV = 1.
When the PLL reference signal comes from the separator, the PLL rising edge must be
preferably used in order to not use the PLL coast mode. It should be noted that the
HSYNCO output of the sync separator is always a mostly LOW signal, whatever is the
polarity of the composite sync input. The VSYNCO output signal of the sync separator is
also mostly LOW signal. It is at a high state during the vertical blanking.
8.5 Sync-on-green
When the SOG input is selected (bit SOGSEL = 1), the SOG charge pump current bits
SOGI[1:0] should be programmed in function of the input signal; see Table 5.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TDA8754HL27BE-S | 功能描述:视频模拟/数字化转换器集成电路 3X8 BIT VIDEO A/D-270 MSPS RoHS:否 制造商:Texas Instruments 输入信号类型:Differential 转换器数量:1 ADC 输入端数量:4 转换速率:3 Gbps 分辨率:8 bit 结构: 输入电压:3.3 V 接口类型:SPI 信噪比: 电压参考: 电源电压-最大:3.45 V 电源电压-最小:3.15 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:TCSP-48 封装:Reel |
| TDA8755 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:YUV 8-bit video low-power analog-to-digital interface |
| TDA8755T | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:YUV 8-bit video low-power analog-to-digital interface |
| TDA8755TD-T | 制造商:未知厂家 制造商全称:未知厂家 功能描述:TV/Video Signal Processor |
| TDA8757 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Triple 8-bit ADC 170 Msps |
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