参数资料
型号: TDA8754HL/21/C1
厂商: NXP SEMICONDUCTORS
元件分类: ADC
英文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封装: 20 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, SOT486-1, LQFP-144
文件页数: 17/57页
文件大小: 259K
代理商: TDA8754HL/21/C1
TDA8754_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 3 May 2007
24 of 57
NXP Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msample/s
9.3 Offset registers (R, G and B)
The offset registers contain a 9-bit value which controls the clamp level for the RGB
channels. The 8 LSBs are in the offset registers and the 1 MSB is in the coarse gain
control register. The relationship between the programming code and the level of the
clamp code is given in Table 19. The reset value is: clamp code = 0 and ADC output = 0.
Table 17.
Offset registers (00h, 03h, 06h) bit allocation
Register
7
6
5
4
3
2
1
0
OFFSETR (00h)
OR7
OR6
OR5
OR4
OR3
OR2
OR1
OR0
OFFSETG (03h)
OG7
OG6
OG5
OG4
OG3
OG2
OG1
OG0
OFFSETB (06h)
OB7
OB6
OB5
OB4
OB3
OB2
OB1
OB0
Reset
00000000
Table 18.
Offset registers (00h, 03h, 06h) bit description
Bit
Symbol
Description
OFFSETR (address: 00h)
7 to 0
OR[7:0]
offset R channel; LSB in this register and MSB bit OR8 in register
COARSER
OFFSETG (address: 03h)
7 to 0
OG[7:0]
offset G channel; LSB in this register and MSB bit OG8 in register
COARSEG
OFFSETB (address: 06h)
7 to 0
OB[7:0]
offset B channel; LSB in this register and MSB bit OB8 in register
COARSEB
Table 19.
Coding for clamp level and ADC output
Value
OR8 OR7 OR6 OR5 OR5 OR3 OR2 OR1 OR0 Clamp
code
(decimal)
ADC output
(code transition)
OG8 OG7 OG6 OG5 OG4 OG3 OG2 OG1 OG0
OB8 OB7 OB6 OB5 OB4 OB3 OB2 OB1 OB0
1E9h
1
0
1
0
24
24/23
1EAh
1
0
1
0
1
23
23/22
::
:
1FFh
1
1/0
000h
0
0/1
001h
0
1
+1
1/2
::
:
03Fh
0
1
63
63/64
040h
0
1
0
64
64/65
::
:
078h
0
1
0
120
120/121
079h
0
1
0
1
121
121/122
::
:
080h
0
1
0
128
128/129
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