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| 型号： | TDA8754HL/21/C1 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封装： | 20 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, SOT486-1, LQFP-144 |
| 文件页数： | 7/57页 |
| 文件大小： | 259K |
| 代理商： | TDA8754HL/21/C1 |
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TDA8754_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 3 May 2007
15 of 57
NXP Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msample/s
The reference ladders regulators are integrated.
8.2.4 Clamp
Three independent parallel clamping circuits are used to clamp the video input signals on
programmable black levels. The clamp levels may be set from
24 to +136 LSBs in steps
of 1 LSB. They are controlled by three 9-bit I2C-bus registers (OFFSETR, OFFSETG and
OFFSETB).
The clamp pulse can be generated internally (based on the PLL clock reference) or can
be externally applied on pin CLP.
Remark: To prevent clamp noise when using internal clamp generated by the pixel
counter (bit CLPSEL2 = 0), it is advised to delay the clamp pulse by 16 pixels using the
HSYNCL register.
By setting correctly the I2C-bus bits, it is possible to inhibit the clamp request with the
Vsync signal. This inhibition will be effected by forcing logic 0 on the clamp request output.
It should be noted that the clamp period can start on the falling edge of the clamp request
and that the high level of the clamp request sets the ADC outputs in the blanking mode.
This means that by forcing the clamp signal request to logic 0 by using Vsync, a falling
edge may happen on the clamp request if this signal was at logic 1 before enforcing the
inhibition. To avoid this, the user has to guarantee that the Vsync signal used for the clamp
inhibition will not be set during a high level of the clamp request signal.
Remark: If signal Vsync is coming from the external pin VSYNC, this signal may be used
to coast the PLL. In order to properly do the coast, the edge of signal Vsync (COAST)
must not appear at the same time as the edge of signal Hsync. This condition is similar to
the pin CLP inhibition condition.
8.2.5 AGC
Three independent variable gain ampliers are used to provide, for each channel, a
full-scale input signal to the 8-bit ADC. The gain adjustment range is designed in such a
way that for an input range varying from 0.5 to 1 V (p-p), the output signal corresponds to
the ADC full-scale input of 1 V (p-p).
8.3 HSOSEL, DEO and SCHCKREFO
Bit HSOSEL allows to have a full correlation phase behavior between outputs CKDATA
and HSYNCO when bit HSOSEL = 0 (Hsync from counter). If HSOSEL = 0 and bits PA4
to PA0 of register PHASE are changed to chose the best sampling time, the phase
relationship between outputs CKDATA and HSYNCO will stay unchanged. After the video
standard is determined, bit HSOSEL must be set to a logic 0 for normal operation mode.
To use the Hsync from the counter the registers HSYNCL, HBACKL, HDISPLMSB and
HDISPLLSB should be set properly in order to create the correct HSYNCO and DEO
output signals (see Figure 5 and Figure 6), which is depending on video standard. Output
signal DEO should be used to determine the rst active pixel.
The demultiplexed mode should be used (bit DMXRGB = 1) and the output ow is
alternated between port A and port B in case the sampling frequency is over
140 Msample/s (clock frequency). It is necessary, in order to warrant that the outputs
HSYNCO and DEO are always changing on CKDATA output rising edge (see Figure 7),
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相关代理商/技术参数 |
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| TDA8754HL27BE-S | 功能描述:视频模拟/数字化转换器集成电路 3X8 BIT VIDEO A/D-270 MSPS RoHS:否 制造商:Texas Instruments 输入信号类型:Differential 转换器数量:1 ADC 输入端数量:4 转换速率:3 Gbps 分辨率:8 bit 结构: 输入电压:3.3 V 接口类型:SPI 信噪比: 电压参考: 电源电压-最大:3.45 V 电源电压-最小:3.15 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:TCSP-48 封装:Reel |
| TDA8755 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:YUV 8-bit video low-power analog-to-digital interface |
| TDA8755T | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:YUV 8-bit video low-power analog-to-digital interface |
| TDA8755TD-T | 制造商:未知厂家 制造商全称:未知厂家 功能描述:TV/Video Signal Processor |
| TDA8757 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Triple 8-bit ADC 170 Msps |
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