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参数资料
| 型号： | TDA8960HB |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封装： | PLASTIC, SOT-319, QFP-64 |
| 文件页数： | 15/36页 |
| 文件大小： | 203K |
| 代理商： | TDA8960HB |
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1999 Jun 14
22
Philips Semiconductors
Preliminary specication
ATSC 8-VSB demodulator and decoder
TDA8960
AC CHARACTERISTICS
VDDD = 3.3 V; VSSD = 0 V; Tamb =25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock (pin CLK)
fclk(sys)
system clock frequency
21.52
MHz
tCLKH
system clock HIGH time
21.23
ns
tCLKL
system clock LOW time
note 1
21.23
ns
A/D interface (pins ADIN[9 to 0])
tsu(A/D)
A/D interface set-up time
5
ns
th(A/D)
A/D interface hold time
5
ns
DAC interface (pins TRSDO, TRCS, TRLD and TRSTB); see Fig.13
tsu(D/A)
D/A interface set-up time
40
ns
th(D/A)
D/A interface hold time
0
ns
Transport stream interface (pins DATA[7 to 0], SOP, ERROR and DATAVALID); see Fig.14
tsu(D)
transport interface data set-up time
5
ns
th(D)
transport interface data hold time
5
ns
tDATACLKL
transport interface DATACLK LOW
time
180
ns
tDATACLKH
transport interface DATACLK HIGH
time
180
ns
tDATCLKW
transport interface DATACLK period
371.7
ns
tDAT-VAL
transport interface DATA to
DATAVALID, ERROR and SOP
0
ns
I2C-bus (pins SDA and SCL); see Fig.10
fSCL
SCL clock frequency
0
400
kHz
tBUF
bus free time between a STOP and
START condition
1.3
s
tHD;STA
hold time (repeated) START
condition; after this period the rst
clock pulse is generated
0.6
s
tLOW
LOW period of the SCL clock
1.3
s
tHIGH
HIGH period of the SCL clock
0.6
s
tSU;STA
set-up time for a repeated START
condition
0.6
s
tSU;STO
set-up time for STOP condition
0.6
s
tHD;DAT
data hold time
0
0.9
s
tSU;DAT
data set-up time
100
ns
tSP
pulse width of spikes which must be
suppressed by the input lter
tbf
tbf
ns
tr
rise time of both SDA and SCL
signals
note 2
20 + 0.1Cb
300
ns
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