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参数资料
| 型号： | TDA8960HB |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封装： | PLASTIC, SOT-319, QFP-64 |
| 文件页数： | 7/36页 |
| 文件大小： | 203K |
| 代理商： | TDA8960HB |
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1999 Jun 14
15
Philips Semiconductors
Preliminary specication
ATSC 8-VSB demodulator and decoder
TDA8960
Boundary scan interface
The TDA8960 Test Access Port (TAP) conforms to
the
“IEEE 1149.1 Joint Test Action Group (JTAG)” standard.
It is used for board level testing of integrated circuits and
for testing the internals of an integrated circuit. The JTAG
standard defines on-chip test logic, which consists of an
instruction register, a group of test data registers including
a bypass register and a boundary scan register, four
dedicated pins collectively called the Test Access Port
(TAP) and a TAP controller.
INSTRUCTION REGISTER
The instruction register consists of four bits without parity.
There are five defined public instructions; see Table 5.
Table 5
Public instruction codes
Notes
1. The bypass instruction provides a minimum length (1-bit) serial path between the TDI and TDO pins when no test
operation is required.
2. This instruction can be used to take a sample of the inputs and outputs during normal operation of the component.
It can also be used to preload data values into the latched outputs of the boundary scan register.
3. This instructions allows testing off-chip circuitry and board level interconnections.
4. This instruction allows low speed, static testing of the on-chip logic. It can also be used after the chip is mounted on
a printed circuit board.
5. This instruction will return the manufacturer ID, part number code and version code. For the TDA8960 the
manufacturer ID is ‘B00000010101’, the part number code is ‘SVSB’ and the version code is ‘D1’.
In addition three private instructions are implemented to control different test modes; see Table 6.
Table 6
Private instruction codes
INSTRUCTION
CODE
SELECTED DATA REGISTER
BYPASS(1)
1111
bypass (initialized state)
SAMPLE(2)
0001
boundary scan
EXTEST(3)
0000
boundary scan
INTEST(4)
0011
boundary scan
IDCODE(5)
0010
identication or bypass
INSTRUCTION
CODE
TEST MODE
SCAN_TEST
1000
test on-chip scan chains
BIST_TEST
1001
BIST test of de-interleaver RAM
RAM_TEST
1010
scan test of the on-chip memories
CHAR_MODE
1011
characterization mode
In the characterization mode the IC is scan-testable in the
same way as in the scan test mode. However the outputs
are not switched to the scan chain outputs. The outputs
retain their functionality. It is now possible to scan test
pattern through the logic and to verify if the timing
constrains at the outputs are met.
EXTERNAL INTERFACE
The TAP consists of five pins as shown in Table 7.
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