参数资料
型号: TE28F008B3B150
厂商: INTEL CORP
元件分类: DRAM
英文描述: SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE
中文描述: 1M X 8 FLASH 3V PROM, 150 ns, PDSO40
封装: 10 X 20 MM, TSOP-40
文件页数: 43/49页
文件大小: 408K
代理商: TE28F008B3B150
E
7.1
SMART 3 ADVANCED BOOT BLOCK
–BYTE-WIDE
43
PRELIMINARY
Reset Operations
IH
V
IL
V
RP# (P)
PLPH
t
IH
V
IL
V
RP# (P)
PLPH
t
(A) Reset during Read Mode
Abort
Complete
PLRH
PHQV
PHWL
PHEL
t
t
t
PHQV
PHWL
t
t
t
(B) Reset during Program or Block Erase, <
PLPH
PLRH
t
t
IH
V
IL
V
RP# (P)
PLPH
t
Abort
Complete
PHQV
PHWL
PHEL
t
t
t
PLRH
t
Deep
Power-
Down
(C) Reset Program or Block Erase, >
PLPH
PLRH
t
0605-17
Figure 16. AC Waveform: Deep Power-Down/Reset Operation
Reset Specifications
V
CC
= 2.7
–3.6V
Symbol
Parameter
Notes
Min
Max
Unit
t
PLPH
RP# Low to Reset during Read
(If RP# is tied to V
CC
, this specification is not
applicable)
1,3
100
ns
t
PLRH
NOTES:
1.
2.
3.
RP# Low to Reset during Block Erase or Program
2,3
22
μs
If t
PLPH
is < 100 ns the device may still RESET but this is not guaranteed.
If RP# is asserted while a block erase or
byte program operation is not executing, the reset will complete within 100 ns.
Sampled but not 100% tested.
相关PDF资料
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