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参数资料
| 型号： | TE28F016B3T120 |
| 厂商： | INTEL CORP |
| 元件分类： | DRAM |
| 英文描述： | SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE |
| 中文描述： | 2M X 8 FLASH 3V PROM, 120 ns, PDSO40 |
| 封装： | 10 X 20 MM, TSOP-40 |
| 文件页数： | 10/49页 |
| 文件大小： | 408K |
| 代理商： | TE28F016B3T120 |
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SMART 3 ADVANCED BOOT BLOCK
–BYTE-WIDE
E
10
PRELIMINARY
The pin descriptions table details the usage of each device pin.
Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions
Symbol
Type
Name and Function
A
0
–A
20
INPUT
ADDRESS INPUTS
for memory addresses. Addresses are internally
latched during a program or erase cycle.
28F008B3: A[0-19], 28F016B3: A[0-20]
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE# and WE# are active. Data is
internally latched. Outputs array, Intelligent Identifier and Status Register
data. The data pins float to tri-state when the chip is de-selected or the
outputs are disabled.
DQ
0
–DQ
7
INPUT/OUTPUT
CE#
INPUT
CHIP ENABLE:
Activates the internal control logic, input buffers,
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels. If
CE# and RP# are high, but not at a CMOS high level, the standby
current will increase due to current flow through the CE# and RP# inputs.
OE#
INPUT
OUTPUT ENABLE:
Enables the device’s outputs through the data
buffers during an array or status register read. OE# is active low.
WE#
INPUT
WRITE ENABLE:
Controls writes to the Command Register and memory
array. WE# is active low. Addresses and data are latched on the rising
edge of the second WE# pulse.
RP#
INPUT
RESET/DEEP POWER-DOWN:
Uses two voltage levels (V
IL
, V
IH
) to
control reset/deep power-down mode.
When RP# is at logic low, the device is in reset/deep power-down
mode
, which drives the outputs to High-Z, resets the Write State
Machine, and draws minimum current.
When RP# is at logic high, the device is in standard operation
.
When RP# transitions from logic-low to logic-high, the device defaults to
the read array mode.
WP#
INPUT
WRITE PROTECT:
Provides a method for locking and unlocking the two
lockable parameter blocks.
When WP# is at logic low, the lockable blocks are locked
,
preventing program and erase operations to those blocks. If a program
or erase operation is attempted on a locked block, SR.1 and either SR.4
[program] or SR.5 [erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked
and
can be programmed or erased.
See Section 3.3 for details on write protection.
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相关代理商/技术参数 |
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|---|---|
| TE28F016B3T150 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE |
| TE28F016B3T90 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| TE28F016B3TA110 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| TE28F016B3TA90 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| TE28F016C3B110 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:3 VOLT ADVANCED+ BOOT BLOCK 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
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