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参数资料
| 型号： | TE28F016B3T120 |
| 厂商： | INTEL CORP |
| 元件分类： | DRAM |
| 英文描述： | SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE |
| 中文描述： | 2M X 8 FLASH 3V PROM, 120 ns, PDSO40 |
| 封装： | 10 X 20 MM, TSOP-40 |
| 文件页数： | 27/49页 |
| 文件大小： | 408K |
| 代理商： | TE28F016B3T120 |
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E
3.5.2
SMART 3 ADVANCED BOOT BLOCK
–BYTE-WIDE
27
PRELIMINARY
AUTOMATIC POWER SAVINGS (APS)
Automatic Power Savings provides low-power
operation during active mode. Power Reduction
Control (PRC) circuitry allows the flash to put itself
into a low current state when not being accessed.
After data is read from the memory array, PRC
logic controls the device’s power consumption by
entering the APS mode where typical I
CC
current is
comparable to I
CCS
. The flash stays in this static
state with outputs valid until a new location is read.
APS reduces active current to standby current
levels for 2.7V–3.6V CMOS input levels.
3.5.3
STANDBY POWER
With CE# at a logic-high level (V
IH
) and the CUI in
read mode, the flash memory is in standby mode,
which disables much of the device’s circuitry and
substantially reduces power consumption. Outputs
(DQ
0
–DQ
7
) are placed in a high-impedance state
independent of the status of the OE# signal. If CE#
transitions to a logic-high level during erase or
program operations, the device will continue to
perform the operation and consume corresponding
active power until the operation is completed.
System engineers should analyze the breakdown of
standby time versus active time and quantify the
respective power consumption in each mode for
their specific application. This will provide a more
accurate measure of application-specific power and
energy requirements.
3.5.4
DEEP POWER-DOWN MODE
The deep power-down mode of the Smart 3
Advanced Boot Block products switches the device
into a low power savings mode, which is especially
important for battery-based devices. This mode is
activated when RP# = V
IL
. (GND
±
0.2V).
During read modes, RP# going low de-selects the
memory and places the output drivers in a high
impedance state. Recovery from the deep power-
down state, requires a minimum time equal to t
PHQV
(see AC Characteristics table).
During program or erase modes, RP# transitioning
low will abort the operation, but the memory
contents of the address being programmed or the
block being erased are no longer valid as the data
integrity has been compromised by the abort.
During deep power-down, all internal circuits are
switched to a low power savings mode (RP#
transitioning to V
or turning off power to the device
clears the status register).
3.6
Power-Up/Down Operation
The device is protected against accidental block
erasure or programming during power transitions.
Power supply sequencing is not required, since
the
device is indifferent as to which power supply, V
PP
or V
CC
, powers-up first.
3.6.1
RP# CONNECTED TO SYSTEM
RESET
The use of RP# during system reset is important
with automated program/erase devices since the
system expects to read from the flash memory
when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU
initialization will not occur because the flash
memory may be providing status information
instead of array data. Intel recommends connecting
RP# to the system CPU RESET# signal to allow
proper CPU/flash initialization following system
reset.
System designers must guard against spurious
writes when V
CC
voltages are above V
LKO
and V
PP
is active. Since both WE# and CE# must be low for
a command write, driving either signal to V
IH
will
inhibit writes to the device. The CUI architecture
provides additional protection since alteration of
memory contents can only occur after successful
completion of the two-step command sequences.
The device is also disabled until RP# is brought to
V
IH
, regardless of the state of its control inputs. By
holding the device in reset (RP# connected to
system PowerGood) during power-up/down, invalid
bus conditions during power-up can be masked,
providing yet another level of memory protection.
3.6.2
V
CC
, V
PP
AND RP# TRANSITIONS
The CUI latches commands as issued by
system
software and is not altered by V
PP
or CE#
transitions or WSM actions. Its default state upon
power-up, after exit from deep power-down mode or
after V
CC
transitions above V
LKO
(Lockout voltage),
is read array mode.
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相关代理商/技术参数 |
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| TE28F016B3T150 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE |
| TE28F016B3T90 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| TE28F016B3TA110 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| TE28F016B3TA90 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| TE28F016C3B110 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:3 VOLT ADVANCED+ BOOT BLOCK 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
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