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参数资料
| 型号： | TFP501PZP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封装： | 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-100 |
| 文件页数： | 21/24页 |
| 文件大小： | 373K |
| 代理商： | TFP501PZP |
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B JULY 2001 REVISED AUGUST 2002
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
RxC+
89
I
Clock positive receiver input—Positive side of reference clock T.M.D.S. low voltage signal differential input
pair.
RxC
90
I
Clock negative receiver input—Negative side of reference clock T.M.D.S. low voltage signal differential input
pair.
SCDT
8
O
Sync detect – Output to signal when the link is active or inactive. The link is considered to be active when DE is
actively switching. The TFP501 monitors the state DE to determine link activity. SCDT can be tied externally to
PDO to power down the output drivers when the link is inactive.
High: active link
Low: inactive link
ST
3
I
Output drive strength select—Selects output drive strength for high or low current drive. (see dc specifications
for IOH and IOL vs ST state.)
High: high drive strength
Low: low drive strength
STAG
7
I
Staggered pixel select – An active low signal used in 2 pixel/clock pixel mode (PIXS = high). Time staggers the
even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels
simultaneously.
High: normal simultaneous even/odd pixel output.
Low: time staggered even/odd pixel output.
VSYNC
47
O
Vertical sync output
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, DVDD, AVDD, OVDD, PVDD
0.3 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, logic/analog signals
0.3 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating ambient temperature range
0
°C to 70°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 10 seconds
260
°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD protection, all pins
2 kV Human Body Model
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JEDEC latch-up (EIA/JESD78)
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VDD (DVDD, AVDD, OVDD, PVDD)
3
3.3
3.6
V
Pixel time, t(pixel) (see Note 1)
6.06
40
ns
Single-ended analog input termination resistance, RT (see Note 2)
45
50
55
Operating free-air temperature, TA
0
25
70
°C
NOTES:
1. t(pixel) is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK is equal to t(pixel) when
in 1-pixel/clock mode and 2 t(pixel) when in 2-pixel/clock mode.
2. The TFP501 is internally optimized using a laser trim process to precisely fix the single-ended termination impedance, RT, to 50
±10%.
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