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参数资料
| 型号： | TLV320ADC3101IRGET320 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC24 |
| 封装： | 4 X 4 MM, GREEN, PLASTIC, VQFN-24 |
| 文件页数： | 49/83页 |
| 文件大小： | 1338K |
| 代理商： | TLV320ADC3101IRGET320 |
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www.ti.com...................................................................................................................................... SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009
Page 0 / Register 45: Interrupt Flags—ADC
READ/
RESET
BIT
DESCRIPTION(1)
WRITE
VALUE
D7
R
0
Reserved
D6
R
0
Left AGC Noise Threshold Flag:
0: Left ADC signal power greater than noise threshold for left AGC
1: Left ADC signal power lesser than noise threshold for left AGC
D5
R
0
Right AGC Noise Threshold Flag:
0: Right ADC signal power greater than noise threshold for right AGC
1: Right ADC signal power lesser than noise threshold for right AGC
D4
R
0
ADC miniDSP engine standard interrupt-port output
D3
R
0
ADC miniDSP engine auxilliary interrupt-port output
D2–D0
R
000
Reserved
(1)
Sticky flag bits. These are read-only bits. They are automatically cleared once they are read and are set only if the source trigger occurs
freshly again.
Page 0 / Register 46: Reserved
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D0
R
XXXX XXXX
Reserved. Do not write to this register.
Page 0 / Register 47: Interrupt Flags—ADC
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R
0
Reserved
D6
R
0
0: Left ADC signal power greater than noise threshold for left AGC
1: Left ADC signal power less than noise threshold for left AGC
D5
R
0
0: Right ADC signal power greater than noise threshold for right AGC
1: Right ADC signal power less than noise threshold for right AGC
D4
R
0
ADC miniDSP engine standard interrupt-port output. This bit indicates the instantaneous value of the
interrupt port at the time of reading the register.
D3
R
0
ADC miniDSP engine auxilliary interrupt-port output. This bit indicates the instantaneous value of the
interrupt port at the time of reading the register.
D2–D0
R
000
Reserved
Page 0 / Register 48: INT1 Interrupt Control
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D5
R
000
Reserved. Do not write any value other than reset value.
D4
R/W
0
0: ADC AGC noise interrupt is not used in the generation of INT1 interrupt.
1: ADC AGC noise interrupt is used in the generation of INT1 interrupt.
D3
R
0
Reserved. Do not write any value other than reset value.
D2
R/W
0
0: Engine-generated interrupts and overflow flags are not used in the generation of INT1 interrupt.
1: Engine-generated interrupts and overflow flags are used in the generation of INT1 interrupt.
D1
R/W
0
0: ADC data-available interrupt is not used in the generation of INT1 interrupt.
1: ADC data-available interrupt is used in the generation of INT1 interrupt.
D0
R/W
0
0: INT1 is only one pulse (active high) of duration typical 2 ms.
1: INT1 is multiple pulses (active high) of duration typical 2 ms and period 4 ms, until flag register 42 or
45 is read by the user.
Copyright 2008–2009, Texas Instruments Incorporated
53
Product Folder Link(s) :TLV320ADC3101
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