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参数资料
| 型号： | TLV320ADC3101IRGET320 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC24 |
| 封装： | 4 X 4 MM, GREEN, PLASTIC, VQFN-24 |
| 文件页数： | 54/83页 |
| 文件大小： | 1338K |
| 代理商： | TLV320ADC3101IRGET320 |
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SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com
Page 0 / Register 84: Right ADC Volume Control
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE(1)
D7
R
0
Reserved. Do not write any value other than reset value.
D6–D0
R/W
000 0000
100 0000 – 110 1000: Right ADC channel volume = 0 dB
110 1000: Rght ADC channel volume = –12 dB
110 1001: Right ADC channel volume = –11.5 dB
110 1010: Rght ADC channel volume = –11.0 dB
...
111 1111: Right ADC channel volume = –0.5 dB
000 0000: Right ADC channel volume = –0.0 dB
000 0001: Right ADC channel volume = 0.5 dB
...
010 0110: Right ADC channel volume = 19.0 dB
010 0111: Right ADC channel volume = 19.5 dB
010 1000: Right ADC channel volume = 20 dB
010 1001– 011 1111 : Reserved. Do not use.
(1)
Values in 2s-complement decimal format
Page 0 / Register 85: Left ADC Phase Compensation
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
1000 0000: Left ADC has a phase shift of –128 ADC_MOD_CLK cycles with respect to right ADC.
1000 0001: Left ADC has a phase shift of –127 ADC_MOD_CLK cycles with respect to right ADC.
...
1111 1110: Left ADC has a phase shift of –2 ADC_MOD_CLK cycles with respect to right ADC.
1111 1111: Left ADC has a phase shift of –1 ADC_MOD_CLK cycles with respect to right ADC.
0000 0000: No phase shift between stereo ADC channels
0000 0001: Left ADC has a phase shift of 1 ADC_MOD_CLK cycles with respect to right ADC.
0000 0010: Left ADC has a phase shift of 2 ADC_MOD_CLK cycles with respect to right ADC.
...
0111 1110: Left ADC has a phase shift of 126 ADC_MOD_CLK cycles with respect to right ADC.
0111 1111: Left ADC has a phase shift of 127 ADC_MOD_CLK cycles with respect to right ADC.
Page 0 / Register 86: Left AGC Control 1
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: Left AGC disabled
1: Left AGC enabled
D6–D4
R/W
000
000: Left AGC target level = –5.5 dB
001: Left AGC target level = –8 dB
010: Left AGC target level = –10 dB
011: Left AGC target level = –12 dB
100: Left AGC target level = –14 dB
101: Left AGC target level = –17 dB
110: Left AGC target level = –20 dB
111: Left AGC target level = –24 dB
D3–D0
R
0000
Reserved. Do not write any value other than reset value.
58
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s) :TLV320ADC3101
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