TOSHIBA
TMPR3904F Rev. 2.0
117
26
10.2
Configuration
10.2.1 TX3904 internal connection
The following Figure 10-1 shows the DMAC connection inside the TX3904.
TX39
Processor Core
Bus ownership release
notice
Bus ownership request
Bus ownership release
request
Bus ownership possession
notice
Control
Address
Data
BUSGNT*
BUSREQ*
BUSREL*
HAVEIT*
DREQ[1:0]DACK[1:0] DREQ[3:2] DACK[3:2]
DMAC0
DMAC1
Fig. 10-1 DMAC Connection Inside TX3904
Inside the TX3904, two DMAC modules are daisy-chain connected. The module closer to the
TX39 Processor Core (of higher priority) is DMAC0 and the module further to it (of lower
priority) is DMAC1.
Each DMAC has two DMA channels; so that the two modules have four channels together.
Each of the channels has a data transfer request signal DREQn from the external devices and an
acknowledge signal DACKn* to the DREQn. The “n” is the channel number and is replaced by
0-3. Channel 0 has a higher priority than Channel 1 and Channel 2 has a higher priority than
Channel 3.
When transferring data, the DMAC can snoop the data cache inside the TX39 Processor Core.
Snooping is a function to make invalid the data inside the data cache when the data of the
transfer destination address are inside the data cache. By doing so, the data inside the data cache
and the data in the external memory are made compatible to each other. The DMAC can select
whether or not to use this snoop function. As for the details of the snoop function, please refer
to “7.5.4. Snoop Function.”
The DMAC has two kinds of bus ownership (GREQ and SREQ) which does/does not use the
snoop function. The GREQ is the bus ownership request that does not use the snoop function
and the SREQ is the bus ownership request that uses the snoop function. Of these two kinds of