参数资料
型号: TMS320C6416TBZLZD1
厂商: Texas Instruments
文件页数: 123/146页
文件大小: 0K
描述: IC FIXED-POINT DSP 532-FCBGA
标准包装: 60
系列: TMS320C6414T/15T/16T
类型: 定点
接口: 主机接口,McBSP,PCI,UTOPIA
时钟速率: 1.0GHz
非易失内存: 外部
芯片上RAM: 1.03MB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: -40°C ~ 90°C
安装类型: 表面贴装
封装/外壳: 532-BFBGA,FCBGA
供应商设备封装: 532-FCBGA(23x23)
包装: 托盘
配用: 701891-ND - KIT STARTER DSP FOR C6416T
TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
78
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
PARAMETER MEASUREMENT INFORMATION
Transmission Line
4.0 pF
1.85 pF
Z0 = 50
W
(see note)
Tester Pin Electronics
Data Sheet Timing Reference Point
Output
Under
Test
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timings.
42
W
3.5 nH
Device Pin
(see note)
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 12. Test Load Circuit for AC Timing Measurements
The tester load circuit is for characterization and measurement of AC timing signals. This load does not indicate
the maximum load the device is capable of driving.
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
Vref = 1.5 V
Figure 13. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX
and VOH MIN for output clocks, VILP MAX and VIHP MIN for PCI input clocks, and VOLP MAX and VOHP MIN for
PCI output clocks.
Vref = VIL MAX (or VOL MAX or
Vref = VIH MIN (or VOH MIN or
VIHP MIN or VOHP MIN)
VILP MAX or VOLP MAX)
Figure 14. Rise and Fall Transition Time Voltage Reference Levels
signal transition rates
All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).
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