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参数资料
型号： TMS320C6416TBZLZD1
厂商： Texas Instruments
文件页数： 29/146页
文件大小： 0K
描述： IC FIXED-POINT DSP 532-FCBGA
标准包装： 60
系列： TMS320C6414T/15T/16T
类型： 定点
接口： 主机接口，McBSP，PCI，UTOPIA
时钟速率： 1.0GHz
非易失内存： 外部
芯片上RAM： 1.03MB
电压 - 输入/输出： 3.30V
电压 - 核心： 1.20V
工作温度： -40°C ~ 90°C
安装类型： 表面贴装
封装/外壳： 532-BFBGA，FCBGA
供应商设备封装： 532-FCBGA（23x23）
包装： 托盘
配用： 701891-ND - KIT STARTER DSP FOR C6416T
TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
124
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 55)
NO.
600
720
850
1G
UNIT
NO.
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
4
tsu(DRV-CKXH) Setup time, DR valid before CLKX high
12
2 12P
ns
5
th(CKXH-DRV)
Hold time, DR valid after CLKX high
4
5 + 24P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or
Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 55)
NO.
PARAMETER
600
720
850
1G
UNIT
NO.
PARAMETER
MASTER§
SLAVE
UNIT
MIN
MAX
MIN
MAX
1
th(CKXH-FXL)
Hold time, FSX low after CLKX high
T 2
T + 3
ns
2
td(FXL-CKXL)
Delay time, FSX low to CLKX low#
H 2
H + 3
ns
3
td(CKXL-DXV)
Delay time, CLKX low to DX valid
2
4
12P + 2.8
20P + 17
ns
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX high
H 2
H + 3
ns
7
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit
from FSX high
4P + 3
12P + 17
ns
8
td(FXL-DXV)
Delay time, FSX low to DX valid
8P + 2
16P + 17
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T =
CLKX period = (1 + CLKGDV) * S
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
# FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
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