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参数资料
| 型号： | TMS470R1B768PGEQR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封装： | PLASTIC, LQFP-144 |
| 文件页数： | 24/49页 |
| 文件大小： | 552K |
| 代理商： | TMS470R1B768PGEQR |
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Switching Characteristics over Recommended Operating Conditions for External Clocks
(1) (2) (3)
CLKOUT
tw(COH)
tw(COL)
ECLK
tw(EOH)
tw(EOL)
SPNS108B – AUGUST 2005 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
SYSCLK or MCLK(4)
0.5tc(SYS) – tf
tw(COL)
Pulse duration, CLKOUT low
ICLK: X is even or 1(5)
0.5tc(ICLK) – tf
ns
ICLK: X is odd and not 1(5)
0.5tc(ICLK) + 0.5tc(SYS) – tf
SYSCLK or MCLK(4)
0.5tc(SYS) – tr
tw(COH)
Pulse duration, CLKOUT high
ICLK: X is even or 1(5)
0.5tc(ICLK) – tr
ns
ICLK: X is odd and not 1(5)
0.5tc(ICLK) – 0.5tc(SYS) – tr
N is even and X is even or odd
0.5tc(ECLK) – tf
tw(EOL)
Pulse duration, ECLK low
N is odd and X is even
0.5tc(ECLK) – tf
ns
N is odd and X is odd and not 1
0.5tc(ECLK) + 0.5tc(SYS) – tf
N is even and X is even or odd
0.5tc(ECLK) – tr
tw(EOH)
Pulse duration, ECLK high
N is odd and X is even
0.5tc(ECLK) – tr
ns
N is odd and X is odd and not 1
0.5tc(ECLK) – 0.5tc(SYS) – tr
(1)
X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1] bits in the SYS module.
(2)
N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
(3)
CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
(4)
Clock source bits are selected as either SYSCLK (CLKCNTL[6:5] = 11 binary) or MCLK (CLKCNTL[6:5] = 10 binary).
(5)
Clock source bits are selected as ICLK (CLKCNTL[6:5] = 01 binary).
Figure 6. CLKOUT Timing Diagram
Figure 7. ECLK Timing Diagram
30
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TMS470R1B768
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