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| 型号： | TMS470R1B768PGEQR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封装： | PLASTIC, LQFP-144 |
| 文件页数： | 37/49页 |
| 文件大小： | 552K |
| 代理商： | TMS470R1B768PGEQR |
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MULTI-BUFFERED A-TO-D CONVERTER (MibADC)
SPNS108B – AUGUST 2005 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances
the A-to-D performance by preventing digital switching noise on the logic circuitry, which could be present on VSS
and VCC, from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to ADREFLO
unless otherwise noted.
Resolution
10 bits (1024 values)
Monotonic
Assured
Output conversion code
00h to 3FFh [00 for VAI ≤ ADREFLO; 3FFh for VAI ≥ ADREFHI]
Table 10. MibADC Recommended Operating Conditions(1)
MIN
MAX
UNIT
ADREFHI
A-to-D high-voltage reference source
VSSAD
VCCAD
V
ADREFLO
A-to-D low-voltage reference source
VSSAD
VCCAD
V
VAI
Analog input voltage
VSSAD – 0.3
VCCAD + 0.3
V
Analog input clamp current(2)
IAIC
–2
2
mA
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
(1)
For VCCAD and VSSAD recommended operating conditions, see the "Device Recommended Operating Conditions" table.
(2)
Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
Table 11. Operating Characteristics Over Full Ranges of Recommended Operating Conditions(1)(2)
PARAMETER
DESCRIPTION/CONDITIONS
MIN
TYP
MAX UNIT
RI
Analog input resistance
See Figure 18.
250
500
Conversion
10
pF
CI
Analog input capacitance
See Figure 18.
Sampling
30
pF
IAIL
Analog input leakage current
See Figure 18.
–1
1
A
IADREFHI
ADREFHI input current
ADREFHI = 3.6 V, ADREFLO = VSSAD
5
mA
Conversion range over which specified
CR
ADREFHI - ADREFLO
3
3.6
V
accuracy is maintained
Difference between the actual step width
EDNL
Differential nonlinearity error
±1.5
LSB
and the ideal value. See Figure 19.
Maximum deviation from the best straight
line through the MibADC. MibADC
EINL
Integral nonlinearity error
±2.0
LSB
transfer characteristics, excluding the
quantization error. See Figure 20.
Maximum value of the difference
E TOT
Total error/absolute accuracy
between an analog value and the ideal
±2
LSB
midstep value. See Figure 21.
(1)
VCCAD = ADREFHI
(2)
1 LSB = (ADREFHI – ADREFLO)/2
10 for the MibADC
42
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TMS470R1B768
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