参数资料
型号: TPS23757PW
厂商: Texas Instruments
文件页数: 3/39页
文件大小: 0K
描述: IC CTRLR POE PD IEEE 20TSSOP
标准包装: 70
类型: 以太网供电开关(PoE)
应用: 远程外设(工业控制,相机,数据访问)
内部开关:
电流限制: 465mA
电源电压: 0 V ~ 57 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 管件
产品目录页面: 1012 (CN2011-ZH PDF)
其它名称: 296-24949-5

TPS23757
www.ti.com
RECOMMENDED OPERATING CONDITIONS (1)
Voltage with respect to V SS (unless otherwise noted)
SLVS948D – JULY 2009 – REVISED NOVEMBER 2013
MIN
NOM
MAX
UNIT
Input voltage range ARTN, COM, PPD, RTN, V DD , V DD1
0
57
V
V I
Input voltage range APb, V C to [ARTN, COM]
Input voltage range APD, CTL to [ARTN, COM]
Input voltage range CS to [ARTN, COM]
0
0
0
18
V B
2
V
V
V
I
Continuous RTN current (T J ≤ 125°C)
(2)
400
mA
I S
C
Sourcing current, V B
V B capacitance
R BLNK
0
0.08
0
2.5
5
350
mA
μ F
k ?
Synchronization pulse width input (when used)
25
ns
T J
Operating junction temperature range
–40
125
°C
(1)
(2)
ARTN and COM tied to RTN.
This is the minimum current-limit value. PDs should be designed for maximum currents below this value to provide for unit power-draw
tolerance. IEEE 802.3at type 1 and IEEE 802.3-2008 compliant devices should not draw average current greater than 350 mA, or their
class power.
DISSIPATION RATINGS
PACKAGE
PWP (TSSOP-20)
Ψ JT
°C/W (1)
0.7 / 0.45
θ JA
°C/W (2)
135
θ JA
°C/W (3)
74
(1)
(2)
(3)
Thermal resistance junction to case top, low-k / high-k board, natural convection, T J = T TOP + ( Ψ JT x P J ). Use Ψ JT to validate T J from
measurements.
JEDEC method with low-k board (1 signal layer), natural convection.
JEDEC method with high-k board (2 signal – 2 plane layers).
ELECTRICAL CHARACTERISTICS
Unless otherwise noted: CS=COM=APD=CTL=RTN=ARTN, GATE and GAT2 float, R FRS = 68.1 k ? , R BLNK = 249 k ? , DT = V B ,
PPD = V SS , APb open, C VB = C VC = 0.1 μ F, R DEN = 24.9 k ? , R CLS open, 0 V ≤ (V DD , V DD1 ) ≤ 57 V, 0 V ≤ V C ≤ 18 V,
–40°C ≤ T J ≤ 125°C. Typical specifications are at 25°C.
CONTROLLER SECTION ONLY
[V SS = RTN and V DD = V DD1 ] or [V SS = RTN = V DD ], all voltages referred to [ARTN, COM] (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
V C
V CUV
V CUVH
UVLO
V C rising
Hysteresis
(1)
8.7
3.3
9
3.5
9.3
3.7
V
Operating current
V C = 12 V, CTL = V B , R DT = 68.1 k ?
0.7
0.92
1.2
mA
t ST
Bootstrap startup time,
C VC = 22 μ F
Startup current source - I VC
V DD1 = 10.2 V, V C (0) = 0 V
V DD1 = 35 V, V C (0) = 0 V
V DD1 = 10.2 V, V C = 8.6 V
V DD1 = 48 V, V C = 0 V
50
27
0.44
2.7
85
45
1.06
4.8
175
92
1.80
6.8
ms
mA
V B
Voltage
6.5 V ≤ V C ≤ 18 V, 0 ≤ I VB ≤ 5 mA
4.8
5.10
5.25
V
(1)
The hysteresis tolerance tracks the rising threshold for a given device.
Copyright ? 2009–2013, Texas Instruments Incorporated
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