参数资料
型号: TPS54326RGTT
厂商: Texas Instruments
文件页数: 15/29页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 3A 16QFN
标准包装: 250
系列: SWIFT™, D-CAP2™
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.76 V ~ 5.5 V
输入电压: 2 V ~ 18 V
PWM 型: 混合物
频率 - 开关: 700kHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-VFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 16-QFN-EP(3x3)
SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012
LAYOUT CONSIDERATIONS
The following layout guidelines are provided using the PWP 14 pin package as an example. The general
guidelines and routing are also applicable to the QFN 16 pin package. Allowance should be made for the
differences in the package pin configurations.
1. Keep the input switching current loop as small as possible.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching current to flow under the device.
6. Keep the pattern lines for VIN and PGND broad.
7. Exposed pad of device must be connected to PGND with solder.
8. VREG5 capacitor should be placed near the device, and connected PGND.
9. Output capacitor should be connected to a broad pattern of the PGND.
10. Voltage feedback loop should be as short as possible, and preferably with ground shield.
11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND.
12. Providing sufficient via is preferable for VIN, SW and PGND connection.
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
14. If VIN and VCC is shorted, VIN and VCC patterns need to be connected with broad pattern lines.
15. VIN Capacitor should be placed as near as possible to the device.
VCC
INPUT
BYPASS
Additional
Thermal
Vias
CAPACITOR
VCC
VIN
VIN
INPUT
FEEDBACK
RESISTORS
VOUT
VFB
VCC
VIN
BYPASS
CAPACITOR
BOOST
BIAS
CAP
VREG5
SS
GND
VBST
SW1
SW2
CAPACITOR
OUTPUT
VOUT
Connection to
SLOW
START
CAP
PG
EN
EXPOSED
POWERPAD
AREA
PGND1
PGND2
INDUCTOR
OUTPUT
FILTER
CAPACITOR
POWER GROUND
on internal or
bottom layer
ANALOG
GROUND
TRACE
To Enable
Control
Additional
Thermal
Vias
POWER GROUND
VIA to Ground Plane
Etch on Bottom Layer
or Under Component
Figure 14. TPS54326 Layout
Copyright ? 2009–2012, Texas Instruments Incorporated
Product Folder Link(s) : TPS54326
15
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