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| 型号： | TPS54550PWPRG4 |
| 厂商： | Texas Instruments |
| 文件页数： | 10/31页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 6A 16HTSSOP |
| 产品培训模块： | Understanding SWIFT Step Down Dc/Dc Converters |
| 标准包装： | 2,000 |
| 系列： | SWIFT™ |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.9 V ~ 12 V |
| 输入电压： | 4.5 V ~ 20 V |
| 频率 - 开关： | 250kHz，500kHz |
| 电流 - 输出： | 6A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-HTSSOP |
| 配用： | 296-19743-ND - EVALUATION MODULE FOR TPS54550 |
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SLVS623A – MARCH 2006 – REVISED APRIL 2006
VO(PH)
VO(SYNC)
Internal Oscillator
Figure 4. SYNC Output Waveform
www.ti.com
Power Good (PWRGD)
The VSENSE pin is compared to an internal
reference signal. If the VSENSE is greater than 97%
and no other faults are present, the PWRGD pin
presents a high impedance. A low on the PWRGD
pin indicates a fault. The PWRGD pin has been
designed to provide a weak pull-down and indicates
a fault even when the device is unpowered. If the
TPS54550 has power and has any fault flag set, the
TPS54550 indicates the power is not good by driving
the PWRGD pin low. The following events, alone or
in combination, indicate power is not good:
? VSENSE pin out of bounds
Up to 1 mA of current can be drawn for use in an
external application circuit. The VBIAS pin must have
a bypass capacitor value of 1.0 μ F. X7R or X5R
grade dielectric ceramic capacitors are
recommended because of the stable characteristics
over temperature.
Bootstrap Voltage (BOOT)
The BOOT capacitor obtains its charge cycle by
cycle from the VBIAS capacitor. A capacitor and
small value resistor from the BOOT pin to the PH
pins are required for operation. The bootstrap
connection for the high-side driver must have a
bypass capacitor of 0.1 μ F and 24- ? resistor .
?
?
?
?
?
?
Overcurrent
Thermal shutdown
UVLO undervoltage
Input voltage not present (weak pull-down)
Slow-starting
VBIAS voltage is low
Error Amplifier
The VSENSE pin is the error amplifier inverting input.
The error amplifier is a true voltage amplifier with 1.5
mA of drive capability with a minimum of 60 dB of
open-loop voltage gain and a unity gain bandwidth of
2 MHz.
Once the PWRGD pin presents a high impedance
(i.e., power is good), a VSENSE pin out of bounds
condition forces PWRGD pin low (i.e., power is bad)
after a time delay. This time delay is a function of the
switching frequency and is calculated using
Voltage Reference
The voltage reference system produces a precision
reference signal by scaling the output of a
temperature stable bandgap circuit. During
production testing, the bandgap and scaling circuits
+ 1000
?
T
delay
s(kHz)
ms
(5)
are trimmed to produce 0.891 V at the output of the
error amplifier, with the amplifier connected as a
voltage follower. The trim procedure improves the
Bias Voltage (VBIAS)
The VBIAS regulator provides a stable supply for the
internal analog circuits and the low-side gate driver.
regulation, since it cancels offset errors in the scaling
and error amplifier circuits.
10
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