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| 型号： | TPS54550PWPRG4 |
| 厂商： | Texas Instruments |
| 文件页数： | 22/31页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 6A 16HTSSOP |
| 产品培训模块： | Understanding SWIFT Step Down Dc/Dc Converters |
| 标准包装： | 2,000 |
| 系列： | SWIFT™ |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.9 V ~ 12 V |
| 输入电压： | 4.5 V ~ 20 V |
| 频率 - 开关： | 250kHz，500kHz |
| 电流 - 输出： | 6A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-HTSSOP |
| 配用： | 296-19743-ND - EVALUATION MODULE FOR TPS54550 |
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10 –0.9 ?
?
INT
2
(24)
SLVS623A – MARCH 2006 – REVISED APRIL 2006
The measured overall loop response for the circuit is
given in Figure 5 . Note that the actual closed loop
crossover frequency is higher than intended at about
25 kHz. This is primarily due to variation in the actual
values of the output filter components and tolerance
variation of the internal feedforward gain circuitry.
Overall the design has greater than 60 degrees of
phase margin and will be completely stable over all
combiations of line and load variability.
Since R1 is given as 10 k ? and the crossover
frequency is selected as 13 kHz, the desired f INT can
CO
+
www.ti.com
Note that capacitors are only available in a limited
range of standard values, so the nearest standard
value has been chosen for each capacitor. The
measured closed loop response for this design is
BIAS AND BOOTSTRAP CAPACITORS
Every TPS54550 design requires a bootstrap
capacitor, C3 and a bias capacitor, C4. The
bootstrap capacitor must be 0.1 μ F. The bootstrap
capacitor is located between the PH pins and BOOT
pin. In addition, a 24- ? resistor is placed in series
with the bootstrap capacitor. This resistor is used to
slow down the leading edge of the high-side FET
turn on waveform. Using this resistor will dramatically
decrease the amplitude of the overshoot on the
swtching node. The bias capacitor is connected
C6 +
1
2 p R1 ?
INT
(25)
between the VBIAS pin and AGND. The value
should be 1.0 μ F. Both capacitors should be
high-quality ceramic types with X7R or X5R grade
The first zero, f Z1 , is located at 1/2 the output filter LC
corner frequency, so R3 can be calculated from
dielectric for temperature stability. They should be
placed as close to the device connection pins as
possible.
R3 +
1
p C6 ?
LC
(26)
LOW-SIDE FET
C8 +
2 p R1 ?
?
ESR
2 p R
C
The second zero, f Z2 , is located at the output filter LC
corner frequency, so C8 can be calculated from
1
LC (27)
The first pole, f P1 , is located to coincide with the
output filter ESR zero frequency. This frequency is
1
+
ESR OUT (28)
where R ESR is the equivalent series resistance of the
output capacitor.
In this case, the ESR zero frequency is 35.4 kHz,
The TPS54550 is designed to operate using an
external low-side FET, and the LSG pin provides the
gate drive output. Connect the drain to the PH pin,
the source to PGND, and the gate to LSG. The
TPS54550 gate drive circuitry is designed to
accommodate most common n-channel FETs that
are suitable for this application. The SWIFT Designer
Software can be used to calculate all the design
parameters for low-side FET selection. There are
some simplified guidelines that can be applied that
produce an acceptable solution in most designs.
The selected FET must meet the absolute maximum
ratings for the application:
Drain-source voltage (V DS ) must be higher than the
maximum voltage at the PH pin, which is V INMAX +
0.5 V.
R5 +
1
2 p C8 ?
ESR
(29)
Gate-source voltage (V GS ) must be greater than 8 V.
Drain current ( ID ) must be greater than 1.1 x I OUTMAX .
C7 +
8 p R3 ?
The final pole is placed at a frequency above the
closed loop crossover frequency high enough to not
cause the phase to decrease too much at the
crossover frequency while still providing enough
attenuation so that there is little or no gain at the
switching frequency. The f P2 pole location for this
circuit is set to 4 times the closed loop crossover
frequency. The last compensation component value
1
CO (30)
Drain-source on resistance (r DSON ) should be as
small as possible, less than 30 m ? is desirable.
Lower values for r DSON result in designs with higher
efficiencies. It is important to note that the low-side
FET on time is typically longer than the high-side
FET on time, so attention paid to low-side FET
parameters can make a marked improvement in
overall efficiency.
Total gate charge (Q g ) must be less than 50 nC.
Again, lower Q g characteristics result in higher
efficiencies.
22
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