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| 型号： | TPS54550PWPRG4 |
| 厂商： | Texas Instruments |
| 文件页数： | 8/31页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 6A 16HTSSOP |
| 产品培训模块： | Understanding SWIFT Step Down Dc/Dc Converters |
| 标准包装： | 2,000 |
| 系列： | SWIFT™ |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.9 V ~ 12 V |
| 输入电压： | 4.5 V ~ 20 V |
| 频率 - 开关： | 250kHz，500kHz |
| 电流 - 输出： | 6A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-HTSSOP |
| 配用： | 296-19743-ND - EVALUATION MODULE FOR TPS54550 |
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SLVS623A – MARCH 2006 – REVISED APRIL 2006
DETAILED DESCRIPTION
www.ti.com
T + 1.15k
SS_INTERNAL(ms) ?
s(kHz)
Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) system has an
internal voltage divider from VIN to AGND. The
defaults for the start/stop values are labeled VIN and
given in Table 1 . The internal UVLO threshold can
be overridden by placing an external resistor divider
from VIN to ground. The internal divider values are
approximately 320 k ? for the high-side resistor and
125 k ? for the low-side resistor. The divider ratio
(and therefore the default start/stop values) is quite
accurate, but the absolute values of the internal
resistors may vary as much as 15%. If high accuracy
is required for an externally adjusted UVLO
threshold, select lower value external resistors to set
the UVLO threshold. Using a 1-k ? resistor for the
low-side resistor R2 (see Figure 1 ) is recommended.
Under no circumstances should the UVLO pin be
connected directly to VIN.
Table 1 . Start/Stop Voltag e Threshold
Slow Start Enable (SSENA) and Internal Slow
Start
Once the SSENA pin voltage exceeds 0.5 V, the
TPS54550 starts operation. The TPS54550 has an
internal digital slow start that ramps the reference
voltage to its final value in 1150 switching cycles.
The internal slow start time (10% - 90%) is
approximated by the following expression:
(3)
Once the TPS54550 device is in normal regulation,
the SSENA pin is high. If the SSENA pin is pulled
below the stop threshold of 0.5 V, switching stops
and the internal slow start resets. If an application
requires the TPS54550 to be disabled, use open
drain or open collector output logic to interface to the
SSENA pin (see Figure 2 ). The SSENA pin has an
internal pull-up current source. Do not use external
pull-up resistors.
START VOLTAGE
THRESHOLD
STOP VOLTAGE
THRESHOLD
VIN (Default)
UVLO
4.49
1.24
3.69
1.02
Input Voltage Supply
R1
320 k ?
5 μ A
R2
1 k ?
125 k ?
Disabled
CSS
Enabled
Figure 1. Circuit Using External UVLO Function
The equations for selecting the UVLO resistors are:
Figure 2. Interfacing to the SSENA Pin
Extending Slow Start Time
R1 + * 1k W
VIN(start) 1 kW
1.24 V
(R1 ) 1 k W ) 1.02 V
VIN(stop) +
1 k W
(1)
(2)
In applications that use large values of output
capacitance, there may be a need to extend the slow
start time to prevent the startup current from tripping
the current limit. The current limit circuit is designed
to disable the high-side MOSFET and reset the
For applications which require an undervoltage lock
out (UVLO) threshold greater than 4.49 V, external
resistors may be implemented (see Figure 1 ) to
adjust the start voltage threshold. For example, an
application needing an UVLO start voltage of
approximately 7.8 V using Equation 1 , R1 is
calculated to the nearest standard resistor value of
5.36 k ? . Using Equation 2 , the input voltage stop
threshold is calculated as 6.48 V.
internal voltage reference for a short amount of time
when the high-side MOSFET current exceeds the
current limit threshold. If the output capacitance and
load current cause the startup current to exceed the
current limit threshold, the power supply output will
not reach the desired output voltage. To extend the
slow start time and to reduce the startup current, an
external capacitor can be added to the SSENA pin.
The slow start capacitance is calculated using the
following equation:
C SS ( μ F) = 5.55x10 –3 T ss (ms)
8
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